Hi community member,
I have a question about the SPI clock of TIDM-FRAM-EEPROM.
Do you think it is possible to design for faster SPI clock (eg 10 MSPS)?
My customer wants to communicate at speeds faster than 1MSPS.
The Design Guide says:
This design is also designed to support EEPROM emulation with SPI and supports slave clock polarity high with rising edge as the trigger. This example is capable of supporting SPI clocks up to 1 Mbps using the direct memory access (DMA). All MSP430FR5x and MSP430FR6x devices have onboard DMA.
If TIDM-FRAM-EEPROM design is not capable of SPI Clock of 10 MSPS, LPM is considered to be one of the factors.
Do you think that the CPU can support 10MSPS if it is SPI communication in always active mode?
I think it can omit the wake-up time from LPM and interrupt latency.