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# MSP430 - UCS: What is the default of FLLN / FLLD? Frequency of quartz at MSP-TS430PN80USB (4MHz)

Other Parts Discussed in Thread: MSP430F5529, MSP-TS430PN80USB

I try to understand how to use the UCS-FLL. Therefore I am using the mentioned TI sample code above on a MSP430F5529.

I am using a MSP-TS430PN80USB with the following quartzes: XT2 = 1MHz (as delivered), XT1 = 32768Hz (XCAP_2, with no external capacitors).

The comments within the code are explaining that

-  LFXT1 = 32768Hz  --> ACLK

-  LFXT1 --> FLL (default) --> MCLK = 32 * ACLK

-  HFXT2 --> SMCLK

But my oscilloscope shows me:

-  ACLK = 32768Hz,  Pin1.0 (21)  --> correct according to the comments

-  MCLK = 1.0xMHz, Pin7.7 (60)  --> could be correct according to the comments   if 1.0xMHz = 220Hz

-  SMCLK = about 4MHz, Pin2.2 (31)  --> ???

What I don't understand (according to the comments):

-  Why can I read on my oscilloscope that there are 4MHz at Pin2.2  if I am using a 1MHz-quartz as XT2?

Assumptions:

-  Possibility 1:   216Hz = XT1 --> FLL --> MCLK = 222Hz   and   SMCLK = ???            *)   N = 7

-  Possibility 2 :  MCLK = 1MHz   and   216Hz --> FLL --> SMCLK                *) N = 0

*)  As I do not know by sure which default FLLN has got I used the formula

fDCOCLK = D * (N + 1) * (FFLLREFCK / n)    [from users guide p.93, chapter 4.2.6],    where N belongs to FLLN,

to find out what N should be. You can find the answers of my calculations within the assumptions above.

Questions:

- Can anybody confirm that Possibility 2 is right or just put my nose into the right direction?

- I suppose that the default of FLLN = 0 which means N =1. Is this right?

• By default, the MSP-TS430PN80USB target board has a 4Mhz crystal at XT2 and not a 1MHz crystal. This is why 4MHz is seen at P2.2/SMCLK.

The schematic of the target board can be found online: http://www.ti.com/litv/zip/slac314b

Regards,

Bhargavi

• Bob Marley said:
suppose that the default of FLLN = 0 which means N =1. Is this right?

No. Th edefault values of all registers are written in the register description in the family users guide.

For the 5x series, the default values are: FLLD=1 (FDCOCLK/2) and FLLN=31, so FDCOCLK will settle at an average of 62*32768 = 2MHz while MCLK is derived of FDCOCLKDIV which is FDCOCLK/2 due to the FLLD setting.

So the resulting average MCLK is 1.015808MHz. 'Average' because the DCO only has a limited number iof discrete frequencies. The settled frequency is generated by constantly switching between the one below and the one above the target frequency, causing a clock jitter. The typical average values in the datasheet are measured over a period of 5µs.
Using DCOCLKDIV for MCLK averages the jitter a bit.
If the clock is derived from a crystal, then of course there is no clock jitter.

btw: it takes up to 32ms until the FLL has adjusted the DCO to the final value, depending on the factory variation of the device.

As already stated, the default crystal delivered is a 4MHz type. There are also (other) boards with 8 or 16MHz crystals (or none at all)

• Thanks again Jens-Michael Gross

and thank you  Bhargav!

I think now there should be no more questions relating to the UCS for a while.

I will change the name of the headline so there will be no misunderstanding for others.

All the best!

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