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MSP430FR5872: Watchdog Reset occurs but SYSRSTIV does not show reset cause correctly

Part Number: MSP430FR5872


I am using the MSP430FR5872 part on my custom board. It supports a "test watchdog" command via CLI (UART) that puts the firmware into a infinite loop to verify the watchdog functionality.

Here is the sequence used:

1) Board powered up and CLI command issued to test watchdog to put FW in infinite loop

2) As expected few seconds later the watchdog reset occurs and the interrupt vector register (SYSRSTIV) shows the interrupt event as WDTIFG watchdog time-out (PUC) 0x16 on rebooting. We store the value of SYSRSTIV in a local variable in the first instruction in the main() before the watchdog is initialized or started to prevent any possible changes to it.   

3) After rebooting from step 1 we repeat the command to "test watcdog" once more. 

4) Few seconds later the watchdog reset occurs and the interrupt vector register (SYSRSTIV) shows the interrupt event as RSTIFG RST/NMI (BOR) 0x4. The interrupt vector should have shown 0x16 as in step 2. This issue is repeatable.

Can the SYSRSTIV register have both WDTIFG and RSTIFG flags set at the same time ?

The firmware needs to perform certain operations based on the last reset cause and its vital to identify the WDT reset event !

Any suggestions/help would be greatly appreciated. Thanks ! 



  • Hey Aman,

    I think what might be happening is that you are somehow running into nested reset interrupts.  This is discussed a bit in section 1.3.7 of the Family User's Guide: 

    When you read SYSRSTIV, it clears the highest priority interrupt but if there is any other pending interrupt it will be immediate set again.  If you write to SYSRSTIV after reading, it should clear all pending interrupt flags.   

    Can you try just clearing all flags by writing to the register after you read it?  




  • Thanks JD,

    That did the trick ! I am now writing 0 to SYSRSTIV after reading it in order to clear any pending interrupt flags.

    The system now behaves as per expectation.




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