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MSP430F5438: Unable to program MSP430 with microcontroller

Part Number: MSP430F5438
Other Parts Discussed in Thread: MSP-FET,

We have been following http://www.ti.com/lit/ug/slau320ag/slau320ag.pdf to program an MSP430 but don't have a fast enough clock to do it in software.  We are investigating several approaches and would like guidance on best method.

1)  We already have a JTAG/BSCAN block for an FPGA to reuse.  It should be simple to adapt this to program the MSP430 but we're not clear enough on what the behavior of TCLK is supposed to be, or how that changes depending on whether we're using SBW or JTAG.  

2)  A mixed approach where some is handled in SW and other parts are optimized by the FPGA.  Probably simple to develop but unsure which exact parts need changed.

These are our main considerations but would be curious to hear how others have gotten around this in the past.

I see a note that support for  TCLK input on another pin may or may not exist.  Can you elaborate on whether it's possible to control TCLK another way?  If that is the case we would rather switch from SBW to JTAG programming and run TCLK independently with the FPGA.

  • Hi,

    1. It seems that you want to create your own debug simulator to program MSP430? What's your opinion? Why don't you choose to use MSP-FET?

    2. About TCLK problem, the TDI pin is used as TCLK input. You should use FPGA to handle this. It is same to do in our MSP-FET. For more details, you can refer to this:

    Eason

  • We're trying to eliminate the number of devices needed when this SoC is already plugged into the 430.  Have had problems with too long of cables running from the programmer.

    Would it then be correct to say that TCLK should toggle until the rising edge of TCK and then resume its state the next falling edge of TCK?  It'd be preferable to operate outside the state machine and mux TDI and TCLK based on the bus signals.  Is that possible or do we need the state to get the timing precise enough?

  • Nathan Francque said:

    Part Number: MSP430F5438

    We have been following http://www.ti.com/lit/ug/slau320ag/slau320ag.pdf to program an MSP430 but don't have a fast enough clock to do it in software.  We are investigating several approaches and would like guidance on best method.

    If you have all JTAG lines (between master and target device on PCB) available, use JTAG. Anyway, I don't see any problems with SBW, except more complicated shifting functions are used, and signal on SBW_DIO line is fighting with cap on target device RESET pin.

    What is your target device? If target device is F2xx than TCLK during flash erase/write should be between 257 and 476kHz (SBW_DIO pin toggle). TCLK frequency during shifting functions is more or less irrelevant. If target device is F5xx, than there is internal flash clock generator that is used for flash erase/write (TCLK frequency is irrelevant) .

  • Interesting. We have a MSP430F5438. Are you saying TCLK isn't even necessary/used?

  • Nathan Francque said:

    Interesting. We have a MSP430F5438. Are you saying TCLK isn't even necessary/used?

    In this case TCLK is target device MCLK that is not used for generating flash clock, so it is used but value is irrelevant, 0.845 MHz, 1.234 MHz or 3.231 Mhz, whatever, the same.

    You can see in slau320, that flashing F5xx is done by downloading  small flash erase / write function to target device RAM, and than it is executed from there (with irrelevant value of MCLK for function running, released / free running device use internal DCO close to 1 MHz). Data for flashing are sent from master by mailbox system (standard for exchanging data between master and free running target by SBW / JTAG).

  • Nathan Francque said:

    We're trying to eliminate the number of devices needed when this SoC is already plugged into the 430.  Have had problems with too long of cables running from the programmer.

    About this problem I advice you to catch the wave first to see which signal can't setup on time. The solution is to reduce the capacitance or reduce the program speed.

    Nathan Francque said:

    Would it then be correct to say that TCLK should toggle until the rising edge of TCK and then resume its state the next falling edge of TCK?  It'd be preferable to operate outside the state machine and mux TDI and TCLK based on the bus signals.  Is that possible or do we need the state to get the timing precise enough?

    About how to use TCLK to control MSP430, you can refer to this part. It works all on the high state of TCK.

  • Hi,

    Can you give me a background of what you want to do? What you have setup now(the whole system)? All the problems you met?

    Maybe I can give you some advice. It seems that there is a long way until you make it work.

    Eason

  • We are still planning out the simplest way to do this, but only software control has actually been tried.

    It might be simpler to set up a webex.   could also join?

  • I'm having a hard time understanding what all needs to be done here.  How do you load in the flash write program to start?  

    Do you have time to discuss further?

  • Functions for flash erase (slau320w\Targetcode\Funclets\FlashErase\msp430x5xx_FlashPageErase.asm) and write (slau320w\Targetcode\Funclets\FlashWrite\msp430x5xx_FlashWrite.asm) that are downloaded to target device RAM end executed there are written in assembler. Related binary files are slau320w\Replicator430Xv2\FlashErase.c and slau320w\Replicator430Xv2\FlashWrite.c

    You can see how  mass erase is done. Function is copied to target device RAM by WriteMemQuick and started by SetPC. Program will wait some time to function in targed device RAM finish the job. As I already noted, ClrTCLK() and SetTCLK() frequency is irrelevant here, because for 5xx family  there is dedicated flash module clock not related to MCLK .

    //----------------------------------------------------------------------------
    //! \brief This function performs a mass erase (with and w/o info memory) or a
    //! segment erase of a FLASH module specified by the given mode and address
    //! without releasing the device from JTAG control.
    //! Large memory devices get additional mass erase operations to meet the spec.
    //! (Could be extended with erase check via PSA)
    //! \param[in] word Mode (could be ERASE_MASS or ERASE_MAIN or ERASE_SGMT)
    //! \param[in] word Addr (any address within the selected segment)
    void EraseFLASH_430Xv2_wo_release(word EraseMode, unsigned long EraseAddr)
    {
        word loadAddr  = RAM_START_ADDRESS;            // RAM start address specified in config header file
        word startAddr = loadAddr + FlashErase_o[0];   // start address of the program in target RAM
    
        FlashErase_o[2] = (unsigned short)(EraseAddr);     // set dummy write address
        FlashErase_o[3] = (unsigned short)(EraseAddr>>16);
        FlashErase_o[4] = EraseMode;                       // set erase mode
        FlashErase_o[5] = SegmentInfoAKey5xx;               // FCTL3: lock/unlock INFO Segment A
                                                            // default = locked
    
        WriteMemQuick_430Xv2(loadAddr, FlashErase_o_length/2, (word*)FlashErase_o);
      
        {
            word i;
            SetPC_430Xv2(startAddr);
            for (i=110; i--;)
            {
                ClrTCLK();
                SetTCLK();
            }
        }
    
        //max mass/segment erase time for F543x is 32ms
        //do not check mailbox, just wait..
        MsDelay(35);
    
        //let Erase function finish
        {
            word i;
            for (i=110; i--;) //110 to let the erase routine finish the restauration
            {
                ClrTCLK();
                SetTCLK();
            }
        }
    
        SyncJtag_AssertPor();
    
        // clear RAM here - init with JMP $
        {
            word i;
    
            for (i = 0; i < FlashErase_o_length/2; i++)
            {
                WriteMem_430Xv2(F_WORD, loadAddr, 0x3fff);
                loadAddr += 2;
            }
        }
    }

  • Hi, 

    My advice is that you can try to use BSL if you just want to download the code into MSP430. It is much easy than to use SBW or JTAG.

    Here are 2 application reports for your refrence (both are using Sitara process to program MSP430 devices): 

    1. APPLICATION NOTE: Host BSL Driver for Sitara Embedded Linux Host
    2. APPLICATION NOTE: MSP430 ™ Firmware Updates Over I2C Using Linux ®

    Here is to use SimpleLink™ MCUs to program MSP430 devices:

    1. Slaa765 (http://www.ti.com/lit/an/slaa755/slaa755.pdf

    Here is to use MSP430 to program MSP430 devices, there are many choices in this link:

    1. http://www.ti.com/tool/MSPBSL?jktype=recommendedresults

    If you want to use JTAG or SBW port to program MSP430. We have the board MSP430 REP430F for you to reference.  Please refer to following document and example code: 

    1. UG: http://www.ti.com/lit/ug/slau320ag/slau320ag.pdf
    2. Example code: http://www.ti.com/lit/zip/slau320

    Eason

  • So this would download the code, and then over JTAG we write to the flash afterwards?  I see notes about "removing JTAG control" and then polling TDO.  

    Sorry I'm not very familiar with the process, having trouble understanding the documentation.

    Maybe a simpler way of phrasing the question:  We have a Zynq SoC on the board already with a software controlled BSCAN block available to pull in to the FPGA (but standard BSCAN controlled at the drscan/irscan level, i.e. no TCLK etc.). 

    We are looking for the simplest possible approach to program the MSP430 - whether that is entirely in FPGA, entirely in software, or a mix of the two.  

    Our initial thought was that it would be simple to modify or add to the BSCAN block to support to special JTAG functions required for MSP430, but it seems like that may not be the case and we are open to any suggestions.

    Would be happy to exchange information as well if that is easier for you.  Thanks!

  • Hi,

    The JTAG port of MSP430 was designed before the JTAG standard was fixed. That means it is not a standard JTAG on MSP430.

    My advice is that just program the MSP430, choosing BSL needs less work than using JTAG. BSL just need a UART with other two pin.

    You can refer to the link I post before. 

    Eason

  • Unfortunately BSL is not possible for us.  The UART pins are not connected.

  • Ok. The related document that can help you is: 

    1. UG: http://www.ti.com/lit/ug/slau320ag/slau320ag.pdf
    2. Example code: http://www.ti.com/lit/zip/slau320

    I am not an expert on FPGA and JTAG. As a reference, the FPGA in our MSP-FET is only used to implements all kinds of JTAG and SBW shift. TCLK clocks are generated by the FPGA. The MSP430 in the MSP-FET is used to send JTAG/SBW command to FPGA. 

    I think you need to look deep into the code of slau320, and change it according to your requirement.

    Eason

     

  • Eason Zhou said:

    I am not an expert on FPGA and JTAG. As a reference, the FPGA in our MSP-FET is only used to implements all kinds of JTAG and SBW shift. TCLK clocks are generated by the FPGA. The MSP430 in the MSP-FET is used to send JTAG/SBW command to FPGA. 

    Yes, MSP430F5xx 20 MHz device used as heart of MSP-FET is slow for port write / read (needed for shifting), but If FPGA is used only for shift speed-up and not for energy trace related staff, than I disagree on this implementation. There are plenty of low cost micro devices (used as standalone master without glue logic or extra parts) that can provide fast SBW interface.

  • Hi,

    You are right. The engrytrace is also in FPGA to read the register and core state. And there is another G2 device to do PID to control the DC-DC.

    As it has no relationship with  Nathan Francque's application, I didn't mention it. You are really a MSP430 expert.

    Eason

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