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MSP430F5131: How to generate two 400khz clock with 180° phase shift by MSP430?

Part Number: MSP430F5131

Hi MSP430 Expert,

I want to generate two 400khz clock with 180° phase shift by MSP430, high volatge of the clock is 5V, low voltage is 0V. could you please recommend a device and give me code tutorial ?

Kevin

  • Hi Kevin,

    This is all the MSP430 that support 5V I/O.

    This is the code you can refer to. 

    MSP430F51x2_ta0_16.c
    /* --COPYRIGHT--,BSD_EX
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     * All rights reserved.
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     * Redistribution and use in source and binary forms, with or without
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     *    its contributors may be used to endorse or promote products derived
     *    from this software without specific prior written permission.
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     * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
     * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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     * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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     *******************************************************************************
     * 
     *                       MSP430 CODE EXAMPLE DISCLAIMER
     *
     * MSP430 code examples are self-contained low-level programs that typically
     * demonstrate a single peripheral function or device feature in a highly
     * concise manner. For this the code may rely on the device's power-on default
     * register values and settings such as the clock configuration and care must
     * be taken when combining code from several examples to avoid potential side
     * effects. Also see www.ti.com/grace for a GUI- and www.ti.com/msp430ware
     * for an API functional library-approach to peripheral configuration.
     *
     * --/COPYRIGHT--*/
    //*******************************************************************************
    //  MSP430F51x2 Demo - Timer0_A3, PWM TA0.1-2, Up Mode, DCO SMCLK
    //
    //  Description: This program generates two PWM outputs on P3.6,P3.7 using
    //  Timer0_A configured for up mode. The value in CCR0, 512-1, defines the PWM
    //  period and the values in CCR1 and CCR2 the PWM duty cycles. Using ~1.045MHz
    //  SMCLK as TACLK, the timer period is ~500us with a 75% duty cycle on P3.6
    //  and 25% on P3.5
    //  ACLK = n/a, SMCLK = MCLK = TACLK = default DCO ~1.045MHz.
    //
    //                MSP430F51x2
    //            -------------------
    //        /|\|                   |
    //         | |                   |
    //         --|RST                |
    //           |                   |
    //           |      P3.6/PM_TA0.1|--> CCR1 - 75% PWM
    //           |      P3.5/PM_TA0.2|--> CCR2 - 25% PWM
    //
    //  B. Nisarga
    //  Texas Instruments Inc.
    //  Dec 2009
    //  Built with CCS v4 and IAR Embedded Workbench Version: 4.21
    //******************************************************************************
    #include <msp430.h>
    
    int main(void)
    {
      WDTCTL = WDTPW + WDTHOLD;                 // Stop WDT
      
      P3DIR |= BIT6+BIT5;                       // P3.6 and P3.5 output
      P3SEL |= BIT6+BIT5;                       // P3.6 and P3.5 options select
      
      // Configure TA0
      TA0CCR0 = 512-1;                          // PWM Period
      TA0CCTL1 = OUTMOD_7;                      // CCR1 reset/set
      TA0CCR1 = 384;                            // CCR1 PWM duty cycle
      TA0CCTL2 = OUTMOD_7;                      // CCR2 reset/set
      TA0CCR2 = 128;                            // CCR2 PWM duty cycle
      
      TA0CTL = TASSEL_2 + MC_1 + TACLR;         // SMCLK, up mode, clear TAR
    
      __bis_SR_register(LPM0_bits);             // Enter LPM0
      __no_operation();                         // For debugger
    }
    
    

    Eason

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