Not a question - a solution that might help others. It took me a long time to hunt this one down.
In my application, the XT2 oscillator is driving a 16 MHz crystal. It is started after the SVS reports that there is sufficient Vcc to run at 16 MHz.
MCLK was selected to run from XT2 with no division; SMCLK to run from XT2 with divide by 2 to give 8 MHz.
The Timer B7 module was set up to run from SMCLK and it was possible to verify that it was indeed running at 8 MHz.
However, the processor was painfully slow, to the point where simple interrupt routines were taking most of a millisecond.
The clock module carries the following values:
DCOCTL 0xC8: DCO range 6; MOD 8
BCSCTL1: 0x36: XT2OFF = 0 (i.e. XT2 switched on); XTS = 0; DIVA = 3 (div by 8); RSEL = 6
BCSCTL2: 0x8A: SELM = 2 (MCLK from XT2); DIVM = 0 (no division); SELS = 1 (SMCLK from XT2); DIVS = 1 (divide by 2); DCOR = 0 (internal resistor)
BCSCTL3: 0x8C: XT2S = 2 (3 to 16 MHz crystal); LFXT1S = 0 (32768 crystal); XCAP = 3 (12.5 pF); XT2OF = 0; LFXT1OF = 0 (no oscillator faults).
According to the above, MCLK should be running from XT2 with no division, i.e. at 16 MHz. However a MOV.W #addr, R15 was taking 3 microseconds, suggesting a MCLK of 1 MHz.
Then the inspiration:
IFG1: 0x02: Oscillator Fault Interrupt Flag = 1.
After clearing this via the debugger, I had the lively 16 MHz MSP430 that I am accustomed to.
The OFIF appears to force MCLK to run on the DCO, but does not affect SMCLK.
I could not find any reference to this behaviour in the device data sheet or the Family UG.
Hope that this helps somebody.
Ray