CCS/MSP430F5308: Slow ISR response time to a DI port input

Tool/software: Code Composer Studio

-F5308 running XT2 = 8 MHz, takes over 300 us to respond to a rising edge interrupt from an opto-isolated 60Hz AC line zero-crossing pulse (from an H11AA1 IC).
In photos below,
 blue trace is P1.4 toggled by the ISR, 
pink trace is input to P2.0 that is configured as a rising-edge interrupt.  
I realize the risetime is very slow, but assumed the port's Schmitt-trigger inputs can accept that.
Source code follows the photos.  
Thx for anyone's thoughts...
Doug

and at expanded timescale:

Code that demo's the issue follows.  XT2 starts OK, MCLK can be shown to be the expected 8MHz, but long delay from rising pulse to 
response of ISR setting the output is a big problem in the overall application this code subset is from.

#include <msp430.h> 


int main(void)
{
   WDTCTL = WDTPW | WDTHOLD;	// Stop watchdog timer

   P1OUT = 0x00;    //
   P1DIR = 0xFF;    //

   P2OUT = 0x00;    // compiler likes init of port A
   P2DIR = 0x00;    // only Bit 0 is used, as an input
   P2IES = 0x01;    // select rising-edge response
   P2IE  = 0x01;    // enable its interrupt
	
// Set up the XTAL clock on XT2
//**************
   P5SEL |= BIT2|BIT3;               // Port select; XTAL to XT2 pins

   UCSCTL6 &= ~XT2OFF;               // Enable XT2
   UCSCTL3 |= SELREF_2;              // FLLref = REFO
                                     // Since LFXT1 is not used, sourcing
                                     // FLL with LFXT1 can set XT1OFFG flag

   UCSCTL4 |= SELA_2;                // ACLK=REFO,SMCLK=DCO,MCLK=DCO

   // Loop until XT1,XT2 & DCO stabilizes - in this case loop until XT2 settles
   do  // note the "do - while" structure
   {
       UCSCTL7 &= ~(XT2OFFG | XT1LFOFFG | DCOFFG); // Clear XT2,XT1,DCO fault flags
       SFRIFG1 &= ~OFIFG;             // Clear fault flags
   }
   while (SFRIFG1&OFIFG);           // spin 'til osc fault flag ends

   UCSCTL6 &= ~XT2DRIVE0;            // Decrease XT2 Drive according to
                                     // XTALfreq; 00 for 4-8 MHz, 01 for 8-16
   UCSCTL4 |= SELS_5 | SELM_5;       // SMCLK=MCLK=XT2
   UCSCTL5 |= DIVS_1;                // SCLK div by 2

   // following steps direct MCLK onto P4.7, 'scope to conform 8 MHz clock
   PMAPPWD = 0x02D52;       // Enable Write-access to modify port mapping registers
   P4MAP7 = PM_MCLK;        // puts MCLK on P4.7 see UG pgs 431-432, & -5308 spec pg 48
   PMAPPWD = 0;             // Disable Write-Access to modify port mapping registers
   P4DIR |= BIT7;           // MCLK set out to bit 7
   P4SEL |= BIT7;
   while(1)      // loop forever
   {
	  __bis_SR_register(LPM3_bits + GIE);   // sleep; only action happens in P2 ISR
      P1OUT ^= 0x01;          // should never get here; toggle P1.0 if we do
   }
}

// ####  Port 2 ISR - adapted from MSP430F530x_P1_03.c
#pragma vector=PORT2_VECTOR       // This ISR responds to an "AC Sync" DI bit
__interrupt void Port_2(void)
{
   P2IFG &= ~BIT0;        // seems to need this (why? isn't clear automatic?)
   P1OUT ^= 0x10;         // Toggle P1.4 at each Sync pulse
}