Another obscure problem solved: I am sharing this in the hope that it helps somebody.
A new project with a part (F2417) which I have used loads of times before was restarting occasionally with unexpected PUC. This would occur after running for several tens of seconds, but the run time would vary considerably.
Quoting from SLAU144J (MSP430x2xx Family User's Guide):
"The following events trigger a PUC:
- A POR signal;
- Watchdog timer expiration when in watchdog mode;
- Watchdog time security key violation;
- Flash Memory security key violation;
- A CPU instruction fetch from the peripheral address range 0h to 01FFh."
I am using CCS 8.3.1.00004 with the TI-supplied 'boot.c' v4.3.1
I investigated this by setting a breakpoint at the very first instruction in the restart ISR which is the STACK_INIT() macro. This means that the stack is still intact from the PUC event, as is the SR and interrupt flags.
A POR would leave either the PORIFG or RSTIFG flag set in IFG1. Neither flag was set.
Either of the watchdog-triggered events would leave WDTIFG set in IFG1. Again, no flag.
The project does not use the Flash memory controller at all, and in any case the KEYV flag was not set.
The Status Register was clear.
The SP pointed to a location in the assigned stack area, and when the (20-bit) address was assembled, it always pointed to a piece of code which monitors the crystal oscillator XT2, which runs at the maximum specified 16 MHz when the SVS indicates a Vcc of 3.3V or more. As part of this code, BCSCTL3 was refreshed with the appropriate configuration, and it was the write to BCSCTL3 which had just been executed immediately before each PUC.
Now the code tests the value in BCSCTL3 and only writes to it if necessary. Result: no unexpected PUC events.
Ray
