MSP432E401Y: EPI GP mode timing

EPI is set to GP mode.
I want to read 16-bit data without using an address.

EPI clock is set to 60MHz and the figure below shows the waveform of the RD pin(EPI0S29).

As shown in the first picture, 8 outputs are generated at approximately 33ns intervals, followed by a 50ns interval as shown in the second picture.

Why is there a 17ns gap?

In order to use TI ADC14L040, output at regular intervals is required.
Which part do I need to check for?

Below is a part of the source code that modified the epi_sdram_dmareq example to GP mode.

...

MAP_EPIDividerSet(EPI0_BASE, 1); // 60MHz EPI clock, 30MHz RD pin
MAP_EPIModeSet(EPI0_BASE, EPI_MODE_GENERAL);

MAP_EPIConfigGPModeSet(EPI0_BASE,
EPI_GPMODE_CLKPIN |
EPI_GPMODE_CLKGATE |
EPI_GPMODE_ASIZE_NONE |
EPI_GPMODE_DSIZE_16,
0, 0);

MAP_EPIAddressMapSet(EPI0_BASE,
EPI_ADDR_PER_SIZE_64KB |
EPI_ADDR_PER_BASE_A);

while(EPI0->STAT & EPI_STAT_INITSEQ)
{ }

MAP_EPIFIFOConfig(EPI0_BASE, EPI_FIFO_CONFIG_RX_1_8); // EPI_FIFO_CONFIG_RX_1_2);
MAP_EPINonBlockingReadConfigure(EPI0_BASE, 0, EPI_NBCONFIG_SIZE_16, 0xA0000000);
MAP_EPIIntEnable(EPI0_BASE, EPI_INT_DMA_RX_DONE);
MAP_IntEnable(INT_EPI0);

MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_UDMA);
while(!(SysCtlPeripheralReady(SYSCTL_PERIPH_UDMA)))
{ }

MAP_uDMAEnable();
MAP_uDMAControlBaseSet(pui8ControlTable);
MAP_uDMAChannelAssign(UDMA_CH20_EPI0RX);

MAP_uDMAChannelAttributeDisable(UDMA_CH20_EPI0RX,
UDMA_ATTR_ALTSELECT | UDMA_ATTR_USEBURST |
UDMA_ATTR_HIGH_PRIORITY |
UDMA_ATTR_REQMASK);

MAP_uDMAChannelControlSet(UDMA_CH20_EPI0RX | UDMA_PRI_SELECT,
UDMA_SIZE_16 | UDMA_SRC_INC_NONE | UDMA_DST_INC_16 |
UDMA_ARB_1024); // UDMA_ARB_1);

MAP_uDMAChannelTransferSet(UDMA_CH20_EPI0RX | UDMA_PRI_SELECT,
UDMA_MODE_PINGPONG,
(void *)&EPI0->READFIFO0, (void *)&internalReadBuf,
sizeof(internalReadBuf)/2);

MAP_uDMAChannelEnable(UDMA_CH20_EPI0RX);

MAP_EPINonBlockingReadStart(EPI0_BASE, 0, 128);