If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

# MSP430F5359: MSP430F5359 DCO and System CLK

Part Number: MSP430F5359

Hi Team

I want to confirm some details with you which list below

1. MSP430F5359 datasheet describe that , System CLK up to 20MHz , DCO max 130MHz,  DCOCLK frequency divided by 1, 2, 4, 8, 16, or 32 within the FLL block. MCLK can be divided by 1, 2, 4, 8, 16, or 32. MCLK is used by the CPU and system.

That means if we use the DCO frequency , we must divide it and let the system CLK<20M ?

2. DCO frequency is set by  DCORSEL, DCO, and MOD bits , then the fDCOCLK = D × (N + 1) × (fFLLREFCLK ÷ n) , If we want to increase the system CLK , which source can be reference , for example , system CLK = DCO/n  or =FLL/n.

Best regards,

Leon.liu

• Hi Leon.liu,

1. The MSP430F5359 is specified for maximum 20MHz operation at VCore 3. The fact that the DCO is able to operate much faster than the CPU, does not necessarily mean, that it makes sense to operate it above the 20MHz, and then divide the clock to lower frequencies. The DCO should be operated from a stable reference, e.g. a 32kHz crystal. this way it would deliver over multiple periods a crystal referenced high frequency. This could be as well 20MHz precisely. The dividers are used rather in cases, where e.g. for the SMCLK you would need a 20MHz but for power consumption reasons the CPU should operate with 10MHz only, but both running synchronously from same clock source.

2. I am not sure, whether I understand your second question exactly. If it's about a scenario as described above, where SMCLK has to operate at a higher clock frequency as CPU/MCLK, but synchronously, then the divider solution would be the scenario, using e.g. 32kHz referenced DCO sourcing SMCLK and MCLK.

Best regards

Peter

• Hi Peter

I am sorry that I did not describe the 2nd question clearly .

I mean that If we do not change the external crystal , how can we enhance the system CLK

Modify the DCORSELx, DCOx , MODx  value to let the DCO running in higher frequency or we need to increase the DCOCLKDIV frequency ?

Because in the datasheet 5.20 DCO Frequency , it looks like the DCO frequency is set by DCORSELx, DCOx , MODx ,but in the user guide , it provide the

formula fDCOCLK = D × (N + 1) × (fFLLREFCLK ÷ n)  and  fDCOCLKDIV = (N + 1) × (fFLLREFCLK ÷ n) ,and MCLK and SMCLK are sourced from

DCOCLKDIV, providing a clock frequency DCOCLK/D, D default is 2 .

It seems like 2 different relation , If I had misunderstand the user guide , please tell me the correct method of enhance the system CLK.

Thanks

Best regards,

Leon.liu

• Hi Leon.liu,

many thanks for the additional explanations. Sorry for the delay in my response.

The principle of the DCO operation, when using the FLL, means active FLL regulation loop is not to touch the DCO/MOD/RSEL settings during operation of the FLL, although they indeed, as you indicated influence an control the DCO frequency. But the principle when having the FLL active is letting the FLL independently of the CPU and executed code, to control and regulate the DCO frequency by the FLL based on the comparison of the selected reference frequency, in the formulas referenced as "fFLLREFCLK". The output of the DCO/FLL system is then kept stable by the FLL, and the DCO/MOD bits are adjusted automatically by the FLL according to the register settings, derived from the above formulas. As visible from the block diagram in the User's Guide, one can use the FLL output divided by 2 or also the direct frequency, means 1/1. The 1/2 operation has the advantage to inherently suppress some potential duty cycle shifts in the output signal.

Dependent on which mode you're using, you of course need to pick the one or the other formula. The results of the formula is setting the target for the FLL, which it regulates to.

Best regards

Peter