Thank you for your help.
I want to confirm some details with you which list below
1. MSP430F5359 datasheet describe that , System CLK up to 20MHz , DCO max 130MHz, DCOCLK frequency divided by 1, 2, 4, 8, 16, or 32 within the FLL block. MCLK can be divided by 1, 2, 4, 8, 16, or 32. MCLK is used by the CPU and system.
That means if we use the DCO frequency , we must divide it and let the system CLK<20M ?
2. DCO frequency is set by DCORSEL, DCO, and MOD bits , then the fDCOCLK = D × (N + 1) × (fFLLREFCLK ÷ n) , If we want to increase the system CLK , which source can be reference , for example , system CLK = DCO/n or =FLL/n.