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MSP430F5131: Flash operations and SYSRIVECT

Thilo Schulz
Prodigy 230 points
Part Number: MSP430F5131

According to slau208q 7.3.3, "interrupts are automatically disabled during any flash operation". My understanding from reading slau208q is that this is facilitated by the flash memory controller always returning the 0x3FFF (JMP PC) instruction while the BUSY flag is set in FCTL3 register.

slau208q 1.3.6.1 says that the interrupt vector table can be moved to RAM using the SYSRIVECT flag.

Let us now assume that the SYSRIVECT flag is set, and the ISR function for a non-mutable interrupt is kept in RAM also. Is my understanding correct, that in this case this ISR will in fact not be disabled and execute on incoming interrupts during both flash erase and write operations?

  • 0
    TI__Expert 7365 points

    Hi Thilo,

    That is correct. As long as the ISR function is also in RAM and the function itself is not accessing Flash, it should execute.

    Srinivas

  • 0 in reply to Srinivas Lingam
    Prodigy 230 points

    Thank you. I suggest documenting this behaviour in slau208 7.3.3, as interrupts are not, in fact, disabled by flash operations.

    I was asking for the case of non-mutable interrupts specifically, as those are not disabled by ISR entry.

    If a mutable interrupt occurs that jumps to an ISR in flash, all subsequent mutable interrupts will be blocked until the flash operation has finished, even those with ISR in RAM.

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