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MSP430F5338: The effect on the adjacent pins when the GIPO pin suddenly changes from high to low

Expert 2785 points
Part Number: MSP430F5338

Hi experts,

Please tell me about the GPIOs of MSP430.

Q1:If P3.0 suddenly changes from high to low, is it possible for P3.1 to be affected by the internal circuitry and thus change the state of the pins?

My customer currently has the following circuit configuration: CPU PCB with an additional SW PCB.The capacitors are installed for noise reduction.

When S6 connected to P3.0 is turned on, P3.1 is momentarily lowered. The following figure shows the waveform when the problem occurs and the waveform when it is normal.

However, when S3 is set to ON, the waveform is "normalcy".
Even if C1, 2 and 3 are deleted and S6 is turned on, the waveform is "normalcy".

I suspect the layout on the "SW PCB" side, but I would like to confirm the effect on the MSP430 side.
If it is not the effect of MSP430, I would appreciate it if you could tell me other possible causes of the problem.

Best regards,

  • Hi O.H., 

    Are you enabling and setting the internal pullup resistors on P3.0 - P3.2?

    P3REN |= BIT0 + BIT1 + BIT2;

    P3OUT |= BIT0 + BIT1 + BIT2;

  • Hi Aaron Barrera,

    I don't know about the customer's register settings.I assume they probably don't use an internal pull-up register, but I'll check with them.

    How does your view differ depending on the presence or absence of an internal pull-up register?

    Best regards,

  • 100nF seems a bit large for noise reduction. Especially since shorting them out with those switches is going to create large current spikes traveling various places.

    All those ground symbols cover a multitude of problems. With those current spikes the details are going to matter.

  • "I suspect the layout on the "SW PCB" side, but I would like to confirm the effect on the MSP430 side.
    If it is not the effect of MSP430, I would appreciate it if you could tell me other possible causes of the problem."

    The first thing I would check is the measurement tools. In particular, a poor ground to a scope probe or analyzer
    could readily produce such an artifact.  Adjust the pullup (or add one) and see if the slope of the recharge changes.
    Test if the effect can be reproduced on other pin combinations.

    If there's NO pullup, then "no wonder".  The port pins might float high, but they are not really high, and stray
    electrical noise could affect them.  The capacitors are big, so you're dumping a lot of current to ground with each button push.

    The ports on the MSP430 are solid, this behavior is not something seen on other installations.

  • Hi O.H., 

    As mentioned by Bryce, leaving the input pins floating can make them susceptible to parasitic voltages, i.e. P3.1 going low when P3.0 is asserted low from the switch. Please confirm with customer if they are enabling the pullup resistors on P3.0 - P3.2.

    If pullup resistors aren't the root cause of the problem, we can investigate the capacitance and layout of the boards.

  • Hi everyone,

    Thank you all for your answers and advice.

    I am currently checking with the customer about the internal pull-up resistance, but there has been no response.
    If the internal pull-up resistance is not the cause of the problem, we will try to investigate based on the opinions you gave us.
    If we are still unable to identify the cause, we will post the question again.

    Best regards,

  • Hi Aaron Barrera,

    They are using an internal pull-up resistor.
     →GPIO_setAsInputPinWithPullUpResistor( GPIO_PORT_P3, GPIO_PIN0 + GPIO_PIN1 + GPIO_PIN2 );

    Also, as additional information, if SW6 is turned on with C1~C6 disconnected, the waveform becomes "normalcy".

    Q2:Could you tell me, If you have a possible opinion on the mechanism of this phenomenon?
    For example, as David Schultz36 says, shorting them out by the switch because the capacitance is too large causes a current spike.
    Or, as a result of poor ground routing on the SW PCB, affecting the adjacent pins, etc.

    Q3:I'm thinking of asking them to refer to 2.2 PCB Design and Layout of MSP430 System-Level ESD Considerations (Rev. A) for layout improvements.
    Could you provide me with any other reference material?

    Best regards,

  • Hi O.H.,

    I ran a quick experiment of measuring the inputs when no caps and the 0.1uF caps are used on P3.0-P3.2. Without caps, I did get a slight 0.5V dip in voltage in P3.1 when P3.0 switch was pressed, but not down to 0V as shown in the graph "when a problem occurs". When 0.1uF caps were placed, I got "normalcy". This is expected behavior from the MSP side, so I would expect the problem to be on the PCB side or system implementation.

    Since you said that problems occur when S4-S6 are asserted when when S1-S3 are not asserted, I would suspect the issue to be the chassis ground on SW PCB or distance of the connector between PCBs. Chassis ground can also be a noisy ground, and if the grounding is not optimal on SW PCB or the current loop involves a wire, the larger loop inductance can cause noise coupling or voltage/current spiking, especially if the signal traces for switches are close to each other. One thing you could do to confirm the grounding is measuring if there is a voltage difference between the chassis ground on the CPU PCB and SW PCB. You can also increase the capacitors to >1uF to see if that reduces the voltage spikes. 

  • Hi Aaron Barrera,

    Thank you for your kind support.
    I was not able to have F5338 on hand at the moment, so your verification is very helpful.

    I understood that this is not the expected behavior on the MSP430 side.
    We will be looking into the SW PCB side, including the voltage difference between the CPU PCB and the chassis ground of the SW PCB, and how it behaves with larger capacitor values.

    If another issue arises, we would like to open a new thread.

    Best regards,