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MSP430FR5949: Not receiving UART data on UCA0.

Part Number: MSP430FR5949

Dear Team

I have used the following clock configurations in my co

	  PM5CTL0 &= ~LOCKLPM5;

	  // Startup clock system with max DCO setting ~8MHz
    CSCTL0_H = CSKEY >> 8;                    // Unlock clock registers
    CSCTL1 = DCOFSEL_3 | DCORSEL;             // Set DCO to 8MHz [set to 8M]

    CSCTL2 = SELA__VLOCLK | SELS__DCOCLK | SELM__DCOCLK; //[Aclk, smclk and mclk]

    CSCTL3 = DIVA__1 | DIVS__1 | DIVM__1;     // Set all dividers

    CSCTL0_H = 0;                             // Lock CS registers

The following functionalities are used in my code

1. UART to a GSM controller (working on uart at 115200 bps)

2. Timer for 15 mins (giving me a clear bit at the end of 15 min interval)

3. Key debounce logic (20 ms delay for debounce)

4. Flowrate calculation (every 2 seconds)

For 2 and 4 i am using the same timer configured as follows

TA0CCR0 = 40000;
TA0CTL = TASSEL__SMCLK | MC_0 | TACLR | TAIE; // SMCLK, count mode, clear TAR
      	  	  	  	  	  	  	  	  	  	  	  // enable interrupt

For debounce i am using Timer1 A1 (TA1CCR0 = 8000)

My problem is that while functions 2,3,4 are working seamlessly i cannot seem to receive data on my UART Rx buffer from GSM controller.

However, when i comment the line 

CSCTL3 = DIVA__1 | DIVS__1 | DIVM__1;     // Set all dividers

the uart begins working. However, functions 2,3,4 are compromised (timer bit comes erratically). Can you please help me in understanding what might be going wrong and how i can resolve this?
  • Hi Shubhankar,

    From the Family User's guide (, the clock system register documentation for Section 3.3.4 CTL3 Register, it looks like commenting out the line 

    CSCTL3 = DIVA__1 | DIVS__1 | DIVM__1;

    will set the divider to divide by 8 as the reset value of DIVM is 3.

    Is it possible the UART baud rate registers: (UCOS16 UCBRx UCBRFx UCBRSx) are set based on 1 MHz clock for the baud rate you are working with?


  • At Reset, the DCO is set to 8MHz [FSEL=6, RSEL=0, Ref User Guide (SLAU367P) Table 3-5] and SMCLK and MCLK are set to DCO/8, or 1MHz [Ref Table 3-7]. By setting the dividers you change SMCLK/MCLK to DCO/1=8MHz.

    Timers and UART rates are computed by dividing (in this case) SMCLK, so it sounds as though you computed the timers based on SMCLK=8MHz, but your UART based on SMCLK=1MHz. I suggest you check how you're computing UCA0BRW.