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MSP430F1222: TIMER_A OUT unit in CAPTURE mode

Part Number: MSP430F1222
Other Parts Discussed in Thread: LMC555

Dear Forum,

I would like ask how the TA OUT Unit works in Capture mode? Becasue the user's manual only detailes the operation for compare mode.

In other words: EQUx (EQU changes the OUT unit states such as Reset/Set etc when certain timming event occurs.) signals are ONLY originated from a comparision of TAR and a CCRx or by a Capture event too?



  • A capture wouldn't trigger an EQUx since TAR doesn't "count to" it -- the same as if the CPU were to store that value in the CCR.

    Looking at the TA diagram [Ref User Guide (SLAU049F) Fig 11-1], if, after the capture, TAR then counts (full-circle) back to the captured CCR value, it would trigger an EQUx, but there's no way to see it with CAP=1.

    The one angle I can see is that in (e.g.) the P1.2 pin schematic [Ref data sheet (SLAS361D) p. 30 -- sorry, the figures aren't numbered here] the pin itself is "shared", so I think that if you set CAP=1 with P1DIR=1, you would get a capture when your OUTn transitions based on the CCR value. But you already know the CCR value, so unfortunately, this seems rather redundant. Moreover, there are simpler ways to accomplish this.

    If you can describe your overall goal, I expect someone here will have some suggestions.

  • Hi Bruce, thanks.

    My goal: if capture (from LMC555 TRIG to OUT - used as comparator)->TA  OUT (low latecy) should reset 555 THR to L. (initailly on H) ->to HOLD its OUT not to cause more capture. 555 TRIG input excited by AC signal (zero crossing detector)


  • If I'm understanding your description correctly, it sounds like you want to use the same pin for both input and output (simultaneously). I suspect I'm not understanding your description correctly.

    Ordinarily I would suggest the Comparator for this sort of thing, but -- despite the claims in the first paragraph of UG Chapter 16 -- the data sheet seems to say you don't have one of those. Is using the F1222 a requirement?

  • No, 430 capture input (P1.2 CCI1A): LMC555 Q out, 430 Out (P1.6: TA OUT1): LMC555 Thr pin.

    I wanted this operation:

    '1222 CCI1A is rise edge controlled

    phase #1: '555 Thr=H, AC signal fed to Trig, if signal goes below its internal trig level then Q->H, if above: Q=L (it is important Q=L to generate rise egde for MSP)

    phase#2: there is a trigger event at '555: at CCI1A positive going edge ->CAPTURE, TAR->CCR1, '555 Thr pin should be pulled down to L quickly to HOLD (store) last state (H) of Q preventing further

    interrupts. That's why I wanted to use a hardver siganl rather SW controlled.

    I can use only 1222 device (this is an added function), '555 is placed on a small support PCB attached onto the main PCB.

    How can I prevent SW issues (multiply interrupts due to latency) when only SW code can pull down 555 Thr pin? When execution goes to TA_ISR at first, simply clearing CCIE and/or CAP bits?

  • OK, I see -- you're using two different TA1 pins (with different configurations). The block diagram/pin schematics don't seem to prevent this, but I've never tried it.

    I suspect, though, that you'll keep running into the "count to" requirement; I don't see any trick to avoid that, since the captured CCR1 by definition matches TAR.

    Clearing the CCIE (and setting the Thr pin low as OUT or GPIO) would be the usual way to do this. You won't get another interrupt (call to the ISR) since GIE=0 there. There would be latency -- I usually estimate about 20 CPU clocks to get into the ISR, plus any interference from other ISRs. And you need to decide the criteria for turning CCIE back on later.

  • Yes, at first I also suspected the OUT unit may be affected because when capture takes CCRx=TAR as you also pointed.

    But I did not experienced OUT response when captured.

    I see MSP automatically clears GIE when entering to an IRQ service. Unfortunately if I can control (>L) 555 THR signal inside ISR routine to blocking its output.

    therefore during IRQ latency multiply capture may occur ( I use CCRx value).

    When TA HW senses multiply capture during IRQ latency, Will ISR rutine be executed muliply times only once?

  • If you get multiple captures before you clear CCIFG, you only get one interrupt. COV would be set in this case. As I recall, you end up with the final (not the first) capture value.

  • Thanks. I tried to summarize in a digramm (I hope, correctly - drawn in Word). It seems, in fact I do not need HW control (by TA1 Out unit), IRQ service routine could do this: