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Systme clock in MSP-TS430PN80USB

Other Parts Discussed in Thread: MSP-TS430PN80USB, MSP430F5529

Hello,

I'm using MSP-TS430PN80USB.

What is the system clock in this board ?

Where does it documented ?

Thanks.

  • Hi Zvi,

    the documentation is here http://www.ti.com/lit/pdf/slau278, and the design files are here http://www.ti.com/litv/zip/slac314b (everyting is available on the tools website too http://focus.ti.com/docs/toolsw/folders/print/msp-ts430pn80usb.html).

    What do you mean when talking about System Clock? A 4 MHz crystal (Q2) is mounted on the target board which feeds the PLL for generating the 48MHz USB clock.

    All other clock settings are up to you!

    Rgds
    aBUGSworstnightmare

     

  • Hello,

    I'm using the SMCLK to trigger Timer 0:

    TA0CCTL0 = CCIE;

    TA0CCR0 = 50000;

    TA0CTL = TASSEL_2 + MC_1 + TACLR;

    What is the factor between the 4MHz crystal to this clock ?

    Does CPU gets its clock fomr the 4MHz crystal ? 

    Thanks,

    Zvika.

  • Hi Zvika,

    well, which MSP4305xx are we talking about?

    Well, you programmed the device, so the clock settings are up to you! By default (after a PUC) MCLK = SMCLK = 1.048..MHz.

    Refer to the users manual for more details (http://focus.ti.com/lit/ug/slau208h/slau208h.pdf).

    If you feel uncofortable with the configuration of the UCS, you can use the MSP430F5xx / MPS430F6xx core libraries to ease your life. Find them here http://focus.ti.com/mcu/docs/litabsmultiplefilelist.tsp?sectionId=96&tabId=1502&literatureNumber=slaa448a&docCategoryId=1&familyId=1615

    Rgds
    aBUGSworstnightmare

  • Hello,

    I looked in slau208h.pdf

    It is not clear from the PDF how should I set all relevant registers.

    Is there another PDF describes how to set all MSP430 registers ?

    TI's 28335 for example has a programming manual. Each register is well documented.

    For example:

    1. How can I set the MSP430 to work from XT1 (and not from internal clock).

    2. How can I divide XT1 to 1,2,4 in order to lower the MSP430 power ?

    Thanks,

    Zvika.

  • Hi Zvi,

    slau208h.pdf is the users manual for MSP430F5xx series --> you can find all information you need inside this document (i.e. refer to chapter 29 for the USB module).

    Which device are (intend) you working with?

    Rgds
    aBUGSworstnightmare

  • Hello,

    According to slau208h.pdf, "XT1 in LF mode is selected as the oscillator source for XT1CL"

    1. Does it mean that after power up, the default clock of the MSP430 is XT1 ?

    2. What is LF mode ? There is no explanation of LF or HF in the PDF.

    3. Can MSP430F5529 use 25MHz crystal clock connected to XT1 ? 

    4. What is the connection between XT1 frequency to MSP430 power consumption ?

    Thanks,

    Zvika.

  • Zvi Vered said:
    1. Does it mean that after power up, the default clock of the MSP430 is XT1 ?

    No. YOu missed the onion-like dependency model of the MSP clock system.

    On startup, the XT1 ocillator is configured for the use of a low-freuency clock crystal. It can be reconfigured to support a high-frequency crystal (400kHz to 25MHz and more - the limits are in teh device datasheet, not the family users guide) or external digital clock signal.

    This does not mean that XT1 oscillator is used for anything at all.

    On the MSP, there are oscillators and clocks. An oscillator is an oscillation source. It can be used or not as input signal to one of the three system clocks. MCLK is the clock used for teh CPU and DMA transfers. SMCLK and ACLK are two other system clocks that are used for driving the various modules.

    Not all oscillators are available for driving all three system clocks (on older families, e.g. ACLK could be only driven by XT1 while SMCLK couldn't but could be driven by XT2). Also, there are some special modules which can be clocked directly by an oscillator or even an external por tpin independently from the three system clocks. So do the flash module and the ADC have access to a free-running (not configurable) oscillator for their timing. And the watchdog can not only use SMCLK and ACLK but also some of the oscillators directly - this has to do with the low power modes.

    After power-on, MCLK and SMCLK are configured to run from XT2 and ACLK runs from XT1. Since there might be no crystals on these inputs at all, there is a failsafe fallback mechanism that switches the SMCLK/MCLK to the internal DCO and ACLK to the internal REFO oscillator unless you configure it otherwise or the crystal finally starts oscillating. THis is explained in the failsafe feature section of the users guide.

    Zvi Vered said:
    2. What is LF mode ? There is no explanation of LF or HF in the PDF.

    It is, bu tonly in general. The specifics are found in the device datasheet. Generally, LF mode supports a 32768ht watch crystal and runs on very low power level. It also provides capacitors typically required for these crystals. HF mode supports HF crystals (consuming much mroe power) or resonators. The physically supported range in written in the datasheet but can be determined too from teh register descriptions (The XT1DRIVE setting description talsk about 4-8Mhz with lowest setting and 24-32MHz with highest)

    Zvi Vered said:
    3. Can MSP430F5529 use 25MHz crystal clock connected to XT1 ?

    Yes. If configured for HF mode and maximum drive strength.

    Zvi Vered said:
    4. What is the connection between XT1 frequency to MSP430 power consumption ?

    usually, power consumption increases quadratically with the clock frequency. But the type of code executed, the use of LPM 8low power mdoes) for idle times and many more things greatly influence this. Also, an external crystal consumes more power than using the internal DCO with the same frequency, ye tthe crystal is more precise and stable than the DCO. And, and, and...

  • Jens-Michael Gross said:

    After power-on, MCLK and SMCLK are configured to run from XT2 and ACLK runs from XT1.

    Tiny correction on an excellent post about MSP430 clocking.  After power-on, MCLK and SMCLK are sourced by DCOCLKDIV by default on the 5xx series.  Fields SELS and SELM of UCSCTL4 (for SCLK and MCLK respectively) are both reset to 100b, which is DCOCLKDIV.

    Jeff

  • Jeff Tenney said:
    After power-on, MCLK and SMCLK are sourced by DCOCLKDIV by default on the 5xx series.

    You're completely right. On the other series, there is no DCOCLKDIV (even on the devices which already have an FLL).
    But you're right, the default is DCOCLKDIV and the default for DCOCLKDIV is DCO/2 for the FLL. I had the datasheet open, and I guess I looked onto the wrong row (SELS_4 is the default, while SELS_5 is XT2CLK)

    Four eyes are better than two :)

  • Hi,

    I would like to thank Mr. Gross on the great post about MSP430 clocking.

    I tried to run the following code (MSP430F552x_UCS_04.c) on MSP430F5529 installed on MSP430PN80USB.

    This board has 32768Hz crystal connected to XT1

    void main(void)
    {
      WDTCTL = WDTPW + WDTHOLD;                 // Stop watchdog timer

      P1DIR |= BIT0;                            // ACLK set out to pins
      P1SEL |= BIT0;                              
      P7DIR |= BIT7;                            // MCLK set out to pins
      P7SEL |= BIT7;

      P5SEL |= BIT4+BIT5;                       // Port select XT1
      UCSCTL6 &= ~(XT1OFF);                     // XT1 On
      UCSCTL6 |= XCAP_3;                        // Internal load cap

      // Loop until XT1 fault flag is cleared
      do
      {
        UCSCTL7 &= ~XT1LFOFFG;                  // Clear XT1 fault flags
      }while (UCSCTL7&XT1LFOFFG);               // Test XT1 fault flag
    .....

    }

    When I tried to run the code, the CPU runs the while loop forever.

    It seems that it does not manage to calibrate XT1 clock.

    Can you help ?

    I want to use XT1 as the source for TIMER_A

    What is the role of the code colored in Red ?

    MCLK can be one of the internal clocks.

    Thanks.

     

  • Hello,

    The MSP430PN80USB I have does not contain a crystal for XT1, only 4MHz for XT2.

    When I ran the code in MSP430F552x_UCS_08.c ,  bit XT2OFFG in UCSCTL7 was set to 0 so XT2 is stablized.

    Thanks,

    Zvika.