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MSP430F5172: SVSL reset under LPM3

Part Number: MSP430F5172

Hello,

We have a product that has been running for years. We are in the process of updating the product and have run into a problem while the processor is in LPM3. The sleep mechanisms are extremely similar in both the new and old implementations. We are in the process of adding an LPM4 mode but are also removing inputs etc that are no longer required. In the process of testing the units we came across random triggers occurring, which led to the investigation. To try and understand the issue we reverted to removing most of the new implementation but keeping the io changes, this led us to the following.

The processor enters sleep LPM3 and roughly 140us later it resets. The reset vector has the SVSL bit. We are not changing the Vcore value so I don't believe it to be eratta PMM14, although we are running it in full performance mode.

If we disable SVSLMD the processor does not reset anymore.

Hope you can help. We are stumped at the moment.

  • Hi Conrad,

    Is SVSLMD =0 or 1 the only difference between the scenarios when the device resets (SVSLMD =1) and when it does not reset (SVSLMD = 0)? Just for reference, what is the Vcore value that you are operating it at?

    Srinivas

  • Hi Srinivas,

    Thank you for your reply.

    1. Setting SVSLMD=0 has made our application not reset, with no other changes. 

    2. The Vcore value is set as following: 

    SVSMHCTL		= SVSHFP								|					//Full Performance on High-Side Supervisor enabled
     								SVSHE									|					//High-Side Supervisor enabled
     								SVSHRVL_1							|					//SVS High-Side Reset Voltage set to 1.84V
     								SVSHMD								|					//SVS interrupt flag enabled in LPM2, 3, 4.
     								SVSMHRRL_1;											//SVS and SVM High-Side Release Voltage set to 1.94V
     																								//SVMHFP	- High Performance on Monitor OFF
     																								//SVMHE		- High Side Monitor disabled
     																								//SVSMHACE- Automatic High-Side Control Disabled
    																								//SVMHOVPE- High Side Overvoltage disabled
     																								//SVSMHEVM-	SVS and SVM events not masked
     																								//SVSMHDLYST - SVS/M High-Side Delay Status (Read)
    
     	SVSMLCTL		= SVSLFP								|					//Full Performance on Low-Side Supervisor enabled
     								SVSLE									|					//Low-Side Supervisor enabled
     								SVSLRVL_0							|					//SVS Low-Side Reset Voltage (no datasheet spec)
     								SVSLMD								|					//SVS interrupt flag enabled in LPM2,3,4
     								SVSMLRRL_0;											//SVS and SVM Low-Side Release Voltage
     																								//SVMLFP	- Low Performance on Monitor OFF
     																								//SVMLE		- Low Side Monitor disabled
     																								//SVSMLACE- Automatic low-side control disabled
     																								//SVMLOVPE- Low Side Overvoltage disabled
     																								//SVSMLEVM-	SVS and SVM events not masked
     																								//SVSMLDLYST - SVS/M Low-Side Delay Status (Read)

    
    

    Then some other details I would like to mention: 

    The unit does not reset every time we go to sleep but we can not find a pattern as to when it does reset. We also added a __delay_cycles(200); ahead of going to LPM3 mode and that has also stabilized the system. 

    //SVMLFP - Low Performance on Monitor OFF  //SVMLE - Low Side Monitor disabled  //SVSMLACE- Automatic low-side control disabled  //SVMLOVPE- Low Side Overvoltage disabled  //SVSMLEVM- SVS and SVM events not masked  //SVSMLDLYST - SVS/M Low-Side Delay Status (Read)

  • Hi Conrad,

    Looking at Table 2-3. Recommended SVSH Settings of the Family User's guide (https://www.ti.com/lit/pdf/slau208), you are setting SVSHRVL = 01 & SVSMHRRL = 001. I would like to confirm fSYS < 12 MHz.

    What does __delay_cycles(200) indicate in time? At fSYS = 12 MHz, this is approximately 16.67 us of additional delay. This increased delay could be helping if the issue is related to the Vcore settling time issues. You did indicate you are not changing the Vcore value but wanted to mention this as the delay seems to be helping and any modifications to Vcore will bring in the settling time issue when you are using it in full performance mode (SVSHFP/SVSLFP=1).

    Is it possible to check with SVSHFP/SVSLFP=0? At least, it will confirm that it is not related to the settling time issue of full performance mode?

    Srinivas

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