Hello,
We have a product that has been running for years. We are in the process of updating the product and have run into a problem while the processor is in LPM3. The sleep mechanisms are extremely similar in both the new and old implementations. We are in the process of adding an LPM4 mode but are also removing inputs etc that are no longer required. In the process of testing the units we came across random triggers occurring, which led to the investigation. To try and understand the issue we reverted to removing most of the new implementation but keeping the io changes, this led us to the following.
The processor enters sleep LPM3 and roughly 140us later it resets. The reset vector has the SVSL bit. We are not changing the Vcore value so I don't believe it to be eratta PMM14, although we are running it in full performance mode.
If we disable SVSLMD the processor does not reset anymore.
Hope you can help. We are stumped at the moment.