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MSP430F2418: Errata Rev S , CPU19 bug - product resetting during operations

Part Number: MSP430F2418

Team, 

Customer is experiencing some issues in production with some of their products, and have a few Errata Question(s):

Our products are unexpectedly resetting during operations, and I would like more technical info on MSP430F2418 Errata Rev S , CPU19 bug:

  • Looking at the MSP430F2418 Errata Rev S, for the CPU19 bug, “CPUOFF modification may result in unintentional register read”, I have these question(s):
    • We’re utilizing IAR 6.10.1, so we don’t have the compiler fix in our code. 
    • CPUOFF occurs for all low power modes. 
    • Our product is almost always in LPM3, except when doing something, then goes back to LPM3, after completing said task. 
      • The question is for the Status Register - is that register subject to this bug, i.e. during exiting LPM (which we’re in LPM3 almost all the time), is it subject to having bad register reads? 
      • Can the Status Register, GIE bit unintentionally be turned off or set to 0?

 Additionally, if there’s any other errata or other info. you would like to direct me to in reference to unexpected resets, please do.

Thanks

Viktorija

  • 1. About this bug, I think it means if you have an instruction with an indirect addressed operand after CPUOFF modification, another register maybe read as well.

    2. I don't think it will cause an unexpected reset. I think you can add a work around to test it.

    3. If you think it is caused by old version complier, you can ask customer to use CCS10 for test.. 

    About your questions:

    1. I don't think it will cause a rst. I think customer can look into the reset source to find the reason. But unfortunately, most of them will be reset after POR or PUC.

    2. No, I don't think so, if the device work in spec.

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