Other Parts Discussed in Thread: CC2640R2F, MSP-TS430RHL20, , MSP430WARE
Hi Team,
We have encountered an inconsistent error in using the I2C bus of MSP430FR2512 on MSP-TS430RHL20 when communicating with the CC2640R2F Launchpad. We have probed with an oscilloscope and can confirm that all portions of the I2C transaction are happening correctly.
We have added a line to exit LPM(0 or 4) within the I2C STOP ISR "__bic_SR_register_on_exit(LPM0_bits);".
What we are observing is that the processor will return to the main application where the main program halts awaiting an I2C transaction "__bis_SR_register(LPM0 + GIE);" and the CPUOFF bit within the SR register will remain set. Only clearing every other I2C STOP event.
Furthermore when the CPU does resume running within the main loop the I2C UCSTPIFG bit of the UCG0IFG register is automatically cleared.
The I2C process is configured and executes according to the Multiple Rx and Tx examples within the MSP430WARE Driver Library.
Is there a more appropriate method of insuring the CPUOFF bit is cleared from within the I2C STOP event?
Regards,
Garret