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MSP430F6726A: Regarding dynamic change of SMCLK frequency

user5994067
Intellectual 820 points
Part Number: MSP430F6726A

Hi

SMCLK = 8MHz is created by FLL from XT1 = 32KHz and used as the clock of SD24_B.


SMCLK is also used in other modules such as UART.


This time, I want to lower the frequency of SD24_B SMCLK below 8MHz.


However, other modules using SMCLK are still 8MHz.


Is it possible to set the SMCLK frequency setting in FLL to, for example,

1MHz before starting single conversion of SD24_B, and then return it to 8MHz again after the conversion is completed?

Best Regards,

  • 0
    TI__Expert 7015 points

    Hi, 

    Since the SMCLK can be configured from DCOCLK or DCOCLKDIV, if the DCOCLKDIV (1MHz)=1/8*DCOCLK (8MHz), you can set the SMCLK source to DCOCLKDIV for SD24_B and then switch to DCOCLK after SD conversion. If the UART is set to using 8MHz SMCLK, the UART cannot be used when SMCLK is 1MHz. 

    if DCOCLKDIV cannot be set to 1/8*DCOCLK, and SMCLK source is fixed to come from DCOCLK, you have to configure the DCOCLK to 1MHz for SD24_B and then configure DCOCLK to 8MHz after SD conversion. But this will be introduce the clock stable time latency due to FLL lock time so that the UART communication might be impacted. 

    I found the clock source of SD24_B can be from MCLK. So the best way is to assign MCLK as the SD24_B clock source and assign SMCLK as UART clock source. The MCLK can be set to sourcing from DCOCLK or DCOCLKDIV. Then the UART communication and other peripherals will not be impacted. 

    Thanks, 

    Lixin 

  • 0 in reply to Lixin Chen1
    TI__Expert 7015 points

    Hi, 

    Do you have further questions about this?

    Thanks, 

    Lixin

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