Hello Guys,
Good day.
Our customer is planning to use BSL Entry Sequence at Shared JTAG Pins of MSP430F2274. On the datasheet of the device, it was mentioned on Note (1) at page57 that Tools accessing theSpy-Bi-Wire interface need to wait for the maximum tSBW,Entime after pulling the TEST/SBWCLK pin high before applying the first SBWCLK clock edge.
Should not the 'maximum' read 'minimum'? Note that tSBW,Entime max is 1uS.
Thanks!
Art