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MSP430F5172: I2C RX interrupt enabled at the same time as the DMA is enabled on the same RX interrupt

Dave Israelsen
Prodigy 130 points
Part Number: MSP430F5172

Looking for clarification, to make sure this feature will work in my design....  If the I2C is a slave and I enable the RX interrupt, and at the same time I have the RX DMA enabled, it's my understanding that the RX interrupt will happen but the DMA transfer will not happen until the RX interrupt bit is disable and the interrupt flag bit is set.  Is this correct?

What I'm hoping that I can do, is to setup the DMA memory location after receiving the first byte from the master processor (vectoring to the interrupt will clear the interrupt flag bit).  After decoding the first byte I can set the memory location for the DMA transfer and then clear the interrupt flag enabling the DMA to receive the remainder of bytes feeding in from the master cpu.   Is this a correct understanding?  I was thinking the interrupt bit would be disabled after the DMA memory assignment is made.

Thanks!!   

  • 0
    Guru 88460 points

    I'm not sure user guide (SLAU208Q) Table 11-2 quite says that. While a bit imprecise, it seems to suggest that the dma request is ignored (or equally likely the USCI never sends it) if RXIE is set, not necessarily that a dma request will be sent when RXIE is cleared.

    More to the point it doesn't seem like your proposed tactic helps you much. Since the DA/SA/SZ registers are copied internally when DMAEN is set, you in effect can't change them while the DMA is enabled [Ref Fig.11-3].  Why not just wait to set DMAEN=1 until after you've dealt with the first byte? Then you don't care what Table 11-2 means. (You can use DMALEVEL=1 to avoid the race, which will be present in either case.)

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