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MSP430F5224: MSP430F5224

Part Number: MSP430F5224

Hi,

I have a 24MHz XTAL on XT2.  It is an Epson TSX-3225 24.0000MF15X-AC3 with 15pf CL and ESR of 50Ohms.  I have the clocks set up in the snippet below.  I have the SMCLK connected to XT2 by setting UCSCTL4 to SELM-5 and divide it by 2 by setting UCSCTL5 to DIVs_1.  I have the SMCLK routed out P2.2 so I can probe the clock frequency which I expect to be 12MHz.  Looking at UCSCTL7, I do not see any fault flags. I have also set the drive strength to "11" by setting bits 15 and 14 of  UCSCTL6 to ones.  The registers are also shown below.

The power to the MSP430 is 3.3V and I have set the PMM to the highest level using the SetVCore(1) to SetVCore(3) calls.

 

When I probe the output, I see a very jittery 529.1KHz clock.  When I probe the XTALK I see the 24MHz sine wave with a 278mVpp amplitude centered about 527mV.  I don't see any spec in the datasheet as to the amplitude requirements but it SEEMS as if the XT2 circuitry is driving the XTAL properly.  I have 18pf Load Caps and the signals are routed pretty well.  I have tried 9pf caps as well but the same results.

Any thoughts?

 

 

VOID Init_Clock(VOID)
{

P5SEL |= BIT2+BIT3; // Port select XT2 and XT1


UCSCTL6 |= XT1OFF; // Disable XT1
UCSCTL6 &=~(XT2OFF); // Enable XT2

// Loop until XT1,XT2 & DCO stabilizes - in this case loop until XT2 settles
do
{
UCSCTL7 &= ~(XT2OFFG|XT1LFOFFG|DCOFFG);  // Clear XT2,XT1,DCO fault flags
}while(UCSCTL7&XT2OFFG);


//UCSCTL6 &= ~(XT1DRIVE0+XT1DRIVE1); // Decrease XT1 Drive according to
// expected frequency
UCSCTL4 = SELS_5 + SELM_5 + SELA_2; // SMCLK=MCLK=XT2, ACLK = REFOCLK, 32.768Khz
UCSCTL5 = DIVS_1; // SMCLK = XT2/2 = 12MHz, MCLK = 24MHz

}

 

 

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