MSP430FR6989: RESET_VECTOR

Observed behavior is that doing this assigns the vector entry (address word) to section (e.g.) ".int15", but the linker doesn't know this section name (reset section is called ".reset") so it will be ignored. If you were to find a way to set the section name to ".reset" you'd probably get a link failure for duplicate section or some such.

As a practical matter, the code generated for (any) ISR will not include code to initialize the SP register, so the stack will be (in general) invalid here. This limits considerably what you can do.

The source for the Reset entry point is in the CCS tree (boot.c). I recommend you Not modify this code; at minimum, think carefully whether there is another way to achieve your goal.

[Edit: Fixed typos]

I need to rewrite this question. It's not asking what I need to know.

You could, sort of, do that.

If you can get past the conflict with the C startup code then you have to deal with the stack. gcc has a "naked" attribute that tells the compiler to skip the usual preamble  and postamble stuff like saving registers to the stack. Required here since the stack pointer hasn't been set.

Plus of course your function must not return. Unless it fudged a suitable stack frame.

Note that in some instances a "weak" attribute is available and is used to allow for just this sort of override. So if the library startup code defined the vector with a weak attribute, you could replace it. But then you would be on the hook for all of the startup actions.

I tried a simple version in gcc just to look at the assembler source generated:

        .global new_reset
        .section        __interrupt_vector_reset,"ax",@progbits
        .word   new_reset
        .text
        .type   new_reset, @function
new_reset:
.LFB3:
        .loc 1 43 1 is_stmt 1
; start of function
; attributes: naked interrupt 
; framesize_regs:     0
; framesize_locals:   0
; framesize_outgoing: 0
; framesize:          0
; elim ap -> fp       2
; elim fp -> sp       0
; saved regs:(none)
.L8:
        .loc 1 44 3 discriminator 1
        .loc 1 44 11 discriminator 1
        .loc 1 44 8 discriminator 1
        BR      #.L8

Which is exactly what I expected. The section name even matches the linker script.

Both of your replies implicitly confirm that this vector is not intended to be used for executing a conventional ISR, nor to behave in that way. Thanks for those replies during a weekend, and David, that extra effort is appreciated.

Here's why I asked that question. I'm interested in writing a reset fault handler. It would determine what event had caused the reset, and possibly respond by executing a specific routine. I naturally went to the header file to learn which vector is responsible for reset. I knew about this vector and what it basically does, but my knowledge about it is not complete. For example, when this vector is executed, I do not know how the MCU actually distinguishes which reset to carry out (BOR, POR, PUC). I assume it's built into the interrupt logic, and it can see the specific reset IFG.

My question should have been "Where is the appropriate location for a reset fault handler?" I think that it should be located in main(), since the reset vector, I think, is not intended to execute an ISR. Therefore, I do not think that vector should be forced to do work it wasn't designed to do. What do you think? Am I correct? That's what I am really trying to learn.

P.S. I'm not a guru. One of your coworkers and I were joking around, and it resulted in me becoming a guru.

Reading SYSRSTIV until zero is good advice. I hadn't thought of that.

What's the CTPL code?

CTPL = Compute Through Power Loss

It magically picks up the pieces.