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MSP430FG6426: CTSD16 with single-ended inputs

Part Number: MSP430FG6426

I wish to acquire single-ended signals in ratiometric mode.

I see CTSD16 works with internal VREFBG (1.16V) or external VEREF+ (1,25V). The internal VREFBG can be used externally from pin VREFBG (REFON = REFOUT = 1) with max 1 mA load, right?

All the CTSD16 channell inputs have the in- negative input tied to VR = VREFBG/VFEREF+ when used as single-ended inputs. The VI single-ended input voltage range is from VR-0.8x(VR/GAIN) to VR+0.8x(VR/GAIN).

How can I measure the full dynamic range of a 0÷(k x VR) V single-ended input signal in ratiometric mode with the max bit resolution in offset binary output data format?

  • Hello,

    As for VREFBG your summary appears correct.  1mA max load, and you should add a 1nF cap if you will be using it externally. 

    As for your question about the full dynamic range, I don't fully understand the question.  Are you asking the best configuration if your signal only ranges from 0V to the voltage reference?  

    Thanks,

    JD

  • Thank you, JD.

    As for the full dynamic input range, I don't understand how to measure i.e. 0-3V single-ended input signal on in+ positive input with the in- negative input tied to VR = VREFBG/VFEREF+. Which VR and GAIN should I choose?

  • Hello Vagni,

    I understand now.  Table 8.8.11.3 in the User's guide specifies the Vi,FSR which is the single-ended full-scale input voltage range.  This is what you mentioned in the initial post.  So, depending on you gain setting will determine your input voltage range.  This voltage range will be centered around your Voltage Reference (VR).  

    With a gain of 1, (no gain) your full-scale range is technically 0V to 2x VR (but the performance drops off close to the rails, which is why it recommends staying between .2 VR to 1.8 VR.  

    As for how this signal is reported from the ADC, this can be seen in section 30.2.8.1 of the User's Guide.  For a single-ended input, I would probably use the "offset binary" mode, meaning that the bottom of the input range would be 0x0000 and the top would be 0xFFFF.  

    Does this address your question?  

    Thanks,

    JD

  • Hello JD,

    So, I should condition my 0-3V single-ended input signal to the [0.2*VR/GAIN, 1.8*VR/GAIN] range. This means attenuating and adding an offset to my single-ended input signal, right?

    Instead, I could use the differential input stage and routing to the in- negative input a 0.8*VR/GAIN external signal generated on my board. My 0-3V single-ended input signal should be only attenuated to the [0, 2*0.8*VR/GAIN] range, right?

    Are there other ways to measure a 0-3V single-ended input signal with the CTSD16?

  • Hello Vagni,

    I guess it depends on if you care about the entire signal, mainly the edges of the signal.  If the edges aren't really important, then you don't have to offset your signal at all.  But I think you understand this.  If you use the built-in 1.16V VBREF as your reference, then your effective input voltage range is going to be .23V to 2.09V.  You can slightly increase this range with a higher external reference voltage. 

    I guess another option would be to configure the ADC in differential mode, and just ground one side of it, but this cuts the dynamic range in half (since you're only measuring one side of the differential.)  But it would allow you to measure from 0V to .8 * VR.  In this case, you'd only have to scale your input down and wouldn't need an offset.

    I found a few app notes that may also be useful here:

    Measuring Single-Ended signal with differential SD ACD:   https://www.ti.com/lit/an/sbaa133a/sbaa133a.pdf?ts=1620351677223 

    Common SD ADC FAQ: https://www.ti.com/lit/an/slaa957/slaa957.pdf?ts=1620351385906&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FMSP430FG6426 

    Hope these help.  

    Thanks,

    JD

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