We have a problem with spurious GPIO interrupts on a custom board running MSP430F5438A.
Most Port 1 & 2 pins have PxIE enabled and different PxIES depending on connected peripherals.
Toggling pin P1.2 at ~1KHz accelerates/causes the issue where multiple IFG's on both ports has been set.
By testing/logging the system we've found the following pseudo code sequence when the issue happen.
volatile unsigned int g_cnt = 0;
volatile unsigned char g_save_1 = 0;
volatile unsigned char g_save_2 = 0;
// 1. Main enters low power mode here
__bis_SR_register( LPM3_bits + GIE );
// 2. Port 1 IRQ
__interrupt void Port1( void )
if (P1IFG & 0x04)
P1IFG &= ~0x04;
// P1 registry at this point:
// IN=0x32, OUT=0x32, DIR=0x00, SEL=0x00, REN=0x7A, IES=0x10, IE=0x3E, IFG=0x11
g_save_1 = (P1IFG & P1IE);
P1IFG = 0;
// 3. Port 2 IRQ
__interrupt void Port2( void )
// P2 registry at this point:
// IN=0xAA OUT=0xAA DIR=0x40 SEL=0x00 REN=0xBF IES=0xAA IE=0xBF IFG=0xAA
g_save_2 = (P2IFG & P2IE);
P2IFG = 0;
// 4. Main is back from low power mode here ... both Port 1 & 2 interrupt routines has been executed
if (g_save_1 || g_save_2)
// Take action ...
By measurement we cannot see any real level transitions on pins that would explain the multiple PxIFGs
Does anyone have a suggestion on what could cause this problem?
We have two hardware designs that are schematically identical (to 99%) but mostly differs in layout.
The problem has only been visible on one board design so far ...
Kind regards, TMA