Other Parts Discussed in Thread: MSP-FET
I am working on some legacy code that has been operational for the last 5+ years (since i joined the company) and I noticed on one of our boards with an MSP430F2132, in debug mode, when i stepped over the DISABLE_WATCHDOG routine shown below, it would immediately jump to reset vector.
Watchdog Macros used:
#define WDTCR_INIT() { WDTCTL = (U16)(WDTPW+WDTHOLD+WDTIS1); \
WDTCTL = (U16)(WDTPW+WDTCNTCL+WDTSSEL+WDTIS1); }
#define KICK_WATCHDOG() ( WDTCTL = (U16)(WDTPW+WDTCNTCL+WDTSSEL+WDTIS1) )
#define DISABLE_WATCHDOG() ( WDTCTL = (U16)(WDTPW+WDTHOLD+WDTIS1) )
It seems that the 3rd parameter WDTIS1 (division of selected clock source) is causing the problem. If i remove it, it will execute the expected command to disable the watchdog, however my concern is that this code has been operational for many years and only now it has started to give me some issues.
I use IAR MSP430 IDE and there have been several updates to its compiler and ide over the year (not sure if this could be in any way related)
Is there a reason why WDTIS1 in the Disable Watchdog Macro would force a jump to the reset vector?
Kr,
Alki