Other Parts Discussed in Thread: CC1101, TEST2
Hi,
I have been asked by TI to post a copy of my query here.
I am having some problems with the in-built CC1101 transceiver.As a basis for configuration, I used TI's Smart RF Studio 7 software to select the appropriate values for the internal registers, a list of which is given below.
The transceiver is configured to send and receive packets of a fixed length. I have two PCB's sending and receiving packets between each other. This configuration works for approximately 30-40 minutes before it locks up. The problem appears to be that the transmitter is locking on and I cannot establish why this is happening. On a spectrum analyser this is displayed as continuous carrier at the centre frequency.
Below, I have listed by observations.
1) Reading the TX status shows that there were over 15 bytes available and the system was in TX mode. This is confirmed with a read of the MARCSTATE register.
2) Reading the number of TX bytes in the FIFO showed a value of 0x0C bytes in the TX buffer.
3) I can exit this state by forcing the transceiver to idle and then going back into the receive state.
3) When the two transceivers are working, the RSSI between the units is in the range 77 to 89 and the link quality is in the range 45 to 49.
4) It is interesting to note that Smart RF Studio sets bit 3 of the MCSM0 register, however the datasheet shows this bit to be reserved. Altering this bit stops the transceiver from operation. Can you please clarify.
5) I have also noticed that the transceiver is operating in frequency hopping mode. Whilst the user manual says that there is a frequency hopping mode, it does not tell me how to enable or disable this. Can you please clarify.
Do you have any suggestions?
// Chipcon default RF settings
const RF_SETTINGS defaultRF_Settings = {
0x06, // FSCTRL1 Frequency synthesizer control.
// SmartRF_Studio setting 0x08
// FREQ_IF = 6 - Fif = 152.34375 kHz
0x00, // FSCTRL0 Frequency synthesizer control.
// FREQOFF = 0 - Foffset = 0
0x10, // FREQ2 Frequency control word, high byte.
0xB1, // FREQ1 Frequency control word, middle byte.
0x3B, // FREQ0 Frequency control word, low byte.
// Frequency control word = 0x0010B13B = 1093947
// Center frequency = 433.999969 MHz
0xCA, // MDMCFG4 Modem configuration.
// CHANBW_E = 3
// CHANBW_M = 0 CHAN_BW = 101.5625 kHz
// DRATE_E = 10
// *** // 0xCA : 38.3835 kBaud, 0xC5 : 1.19948kBaud
0x83, // MDMCFG3 Modem configuration.
// DRATE_M = 131 Rdata = 38.3835 kBaud
0x13, // MDMCFG2 Modem configuration.
// SmartRF_Studio setting 0x90
// DEM_DCFILT_OFF = 0 - Filter is on
// MOD_FORMAT = 1 - 2GFSK
// MANCHESTER_EN = 0 - Encoder is off
// SYNC_MODE = 3 - 30/32 sync word bits
0x22, // MDMCFG1 Modem configuration.
// SmartRF_Studio setting 0x00
// NUM_PREAMBLE = 4
// CHAN_SPC_E = 2
0xF8, // MDMCFG0 Modem configuration.
// CHAN_SPC_M = 248 Channel spacing = 199.951172 kHz
0x00, // CHANNR Channel number.
// CHAN = 0 - Channel offset = 0
0x35, // DEVIATN Modem deviation setting (when FSK modulation is
// enabled).
// DEVIATION_E = 3
// DEVIATION_M = 5
// Deviation frequency = 20.62988 kHz
0x56, // FREND1 Front end RX configuration.
// NOTE: Set by SmartRF_Studio
// LNA_CURRENT = 1 - LNA current setting
// LNA2MIX_CURRENT = 1 - PTAT current setting
// LODI_BUFF_CURRENT = 1 - LO buffer current setting
// MIX_CURRENT = 2 - Mixer current setting
0x10, // FREND0 Front end TX configuration.
// NOTE: Set by SmartRF_Studio
// LODIV_BUF_CURRENT_TX = 1 - CTX LO current setting
// PA_POWER = 0 - Index setting = 0
0x18, // MCSM0 Main Radio Control State Machine configuration.
// FS_AUTOCAL = 1 - Calibrate when going from IDLE to
// Rx or Tx
// NOTE: bit 3 is reserved
// PIN_CTRL_EN = 0 - Pin radio control disabled
// XOSC_FORCEW_ON = 0 - XT2 oscillator is off in sleep
// mode
0x16, // FOCCFG Frequency Offset Compensation Configuration.
// FOC_BS_CS-GATE = 0 - No carrier sens lock
// FOC_PRE_K = 2 - Loop gain before sync word = 3k
// FOC_POST_K = 1 - Loop gain after sync word = K/2
// FOC_LIMIT = 2 - Saturation point for freq offset
// compensation = +/-BWchan/4
0x6C, // BSCFG Bit synchronization Configuration.
// BS_PRE_KI = 1 - Clk feedback loop integral gain
// before sync word = 2Ki
// BS_PRE_KP = 2 - Clk feedback loop proportional
// gain before sync word = 2Kp
// BS_POST_KI = 1 - Clk feedback loop integral
// gain after sync word = Ki/2
// BS_POST_KP = 1 - Clk feedback loop proportional
// gain after sync word = Kp
// BS_LIMIT = 0 - No data rate offset compensation
0x43, // AGCCTRL2 AGC control.
// MAX_DVGA_GAIN = 1 - Highest gain setting cannot be
// used
// MAX_LNA_GAIN = 0 - Max possible LNA + LNA2 gain
// MAGN_TARGET = 3 - Digital filter target
// amplitude = 33dB
// 0x40, // AGCCTRL1 AGC control.
0x60, // AGCCTRL1 AGC control.
// AGC_LNA_PRIORITY = 1 - LNA is decreased first then
// LNA2
// CARRIER_SENSE_REL_THR = 0 - Threshold for carrier
// sense is disabled
// CARRIER_SENSE_ABS_THR = 0 - Absolute threshold for
// asserting carrier
// sense = MAGN_TARGET
// setting
0x91, // AGCCTRL0 AGC control.
// HYST_LEVEL = 2 - Medium hysteresis
// Small asymmetric dead zone
// Medium gain
// WAIT_TIME = 1 - No of filter samples = 16
// AGC_FREEZE = 0 - AGC freeze is off
// FILTER_LENGHT = 1 - Channel filter samples = 16
0xE9, // FSCAL3 Frequency synthesizer calibration.
// NOTE: Set by SmartRF_Studio
// FSCAL3[7:6] = 0xC9 = 201 - Iout =
// CHP_CURR_CAL_EN = 2 - Enable charge pump calibration
// stage when 1
// FSCAL3[3:0] = 9 - Iout = 4.7567mA
0x2A, // FSCAL2 Frequency synthesizer calibration.
// NOTE: Set by SmartRF_Studio
// VCO_CORE_H_EN = 1 = Enabled
// FSCAL2 = 10
0x00, // FSCAL1 Frequency synthesizer calibration.
// NOTE: Set by SmartRF_Studio
// FSCAL1 = 0
0x1F, // FSCAL0 Frequency synthesizer calibration.
// NOTE: Set by SmartRF_Studio
// FSCAL0 = 31
0x59, // FSTEST Frequency synthesizer calibration.
// NOTE: Set by SmartRF_Studio
// FSTEST = 0x59
0x81, // TEST2 Various test settings.
// NOTE: Set by SmartRF_Studio
// TEST2 = 0x81
0x35, // TEST1 Various test settings.
// NOTE: Set by SmartRF_Studio
// TEST1 = 0x35
0x09, // TEST0 Various test settings.
// NOTE: Set by SmartRF_Studio
// TEST0[7:2] = 2
// VCO_CAL_EN = 0 - VCO calibration is disabled
// TEST0[0] = 1
// 0x47, // FIFOTHR RXFIFO and TXFIFO thresholds.
0x67, // FIFOTHR RXFIFO and TXFIFO thresholds.
// ADC_RETENTION = 1 - TEST1 = 0x35 and TEST2 = 0x81
// when wakeup from sleep
// CLOSE_IN_RX = 0 - Rx attenuation = 0dB
// FIFO_THR = 7 - Tx FIFO threshold = 33,
// Rx FIFO threshold = 32
0x29, // IOCFG2 GDO2 output pin configuration.
// SmartRF_Studio setting 0x0B
// GDO2_INV = 0 - Output is non inverted
// GDO2_CFG = 0x29 - RF_RDYn
// 0x00, // IOCFG1 GDO1 output pin configuration.
// GDO1_INV = 0 - Output is non inverted
// GDO1_CFG = 0x00 - RX FIFO overflow
0x06, // IOCFG0 GDO0 output pin configuration. Refer to SmartRF® Studio User Manual for detailed pseudo register explanation.
// SmartRF_Studio setting 0x0C
// GDO0_INV = 0 - Output is non inverted
// GDO0_CFG = 0x06 - Assert when sync word has been sent
// or received
// Deassert Optional address check fails
// Deassert RX_FIFO overflows
// Deassert TX_FIFO underflows
0x04, // PKTCTRL1 Packet automation control.
// PQT = 0 - No threshold counter for sync word
// CRC_AUTOFLUSH = 0 - Auto flush is off
// APPEND_STATUS = 1 - Append RSSI, LQI and CRC OK to end
// of Rx packet
// ADR_CHK = 0 - Address check is off
0x04, // PKTCTRL0 Packet automation control.
// SmartRF_Studio setting 0x12
// WHITE_DATA = 0 - White data generator is off
// PKT_FORMAT = 0 - Normal mode
// CRC_EN = 1 - Calculate CRC for Rx and Tx packets
// LENGTH_CONFIG = 0 - Fixed packet length
0x00, // ADDR Device address = 0. Not used
RF_QUEUE_MSG_SZ // PKTLEN Packet length.
};
