MSP430F67641A: Could not set core voltage to its intended 3V

VCore is regulated core power supply output with related capacitor on device VCore pin. Maximum value for VCore is 3 (it is just number value, not volts) and with this maximum value and 3.3V supply device should work on 25 MHz (check device datasheet because some devices from f5xx/6xx family are limited to 20MHz). Voltage on VCore pin is close to 2V (not 3V).

VCore voltage should be increased in steps, one by one, until max value is reached, so check this function SetVCore to find it, if this is already included inside.

Surya Prakash95 said:

From your sample code i use the below to set the core volltage to 3V, but still see the voltage on (Pin-23 VCORE) is always 1.8V limiting the crystal to 8Mhz.

The MSP430F67641A datasheet gives the typical voltage on the VCORE pin at different PMMCOREV settings:

As the datasheet only gives typical values, measuring VCORE = 1.8V for PMMCOREV = 3 isn't necessarily a problem.

Surya Prakash95 said:

SetVCore(3);

Looking at MSP430Ware 3.80.13.03 the SetVCore function is implemented as a while loop which increments the PMMCOREV setting one step at time, and the reset value of PMMCOREV is zero.

While the datasheet only gives the typical value for the VCORE voltage, if you monitor the VCORE voltage as step the SetVCore function in the debugger you should be able to check if the VCORE voltage increments at each step to confirm the SetVCore function is having an effect.

Dear All,

Thanks a lot for your replies. That really made my understanding clear on the core voltage level and that should be fine in my prototype.

Question-1: My most concern out of it was that, using the same code mentioned above to set the crystal to 25Mhz was not working and the clock is forced to 8Mhz. Are there any dependencies if i have to work with the full 25Mhz capacity ?

Surya Prakash95 said:

My most concern out of it was that, using the same code mentioned above to set the crystal to 25Mhz was not working and the clock is forced to 8Mhz.

Can you clarify what is forcing the clock to 8MHz?

Also, the code in the first post is attempting to start XT1, but it was also mentioned that:

Surya Prakash95 said:

external 32khz crystal is not mount and left open

Can you clarify what is connected to the XIN / XOUT pins?

Thanks again for your quick reply.

The Xin/Xout pins are left open unmount. 

Chester Gillon said:

Can you clarify what is forcing the clock to 8MHz?

I am not exactly sure what is forcing the clock to 8. I wanted my application to run at 25Mhz and i use the below code. When i use this code, the maximum clock i could achieve its 8Mhz for some unknown reasons (checked with __delay_cycles). Could you please help if i am using the right code to configure the clock to run at 25Mhz ?

Surya Prakash95 said:

SetVCore(3);
__bis_SR_register(SCG0); /* Disable the FLL control loop */
UCSCTL6 = (UCSCTL6 | XT1DRIVE_3); /* Highest drive setting for XT1 startup */
while (SFRIFG1 & OFIFG)
{
/* Check OFIFG fault flag */
UCSCTL7 &= ~(DCOFFG | XT1LFOFFG | XT2OFFG); /* Clear OSC fault flags */
SFRIFG1 &= ~OFIFG; /* Clear OFIFG fault flag */
}
UCSCTL6 = (UCSCTL6 & ~(XT1DRIVE_3)); /* Reduce drive to something weaker */

UCSCTL0 = 0;
UCSCTL1 = DCORSEL_6; /* Set RSELx for DCO = 25MHz */
UCSCTL2 = FLLD__4;
UCSCTL2 |= (192 - 1); /* Set DCO Multiplier for 25MHz */
/* Set FLL to 32768*4*192 => 25165824Hz */
__bic_SR_register(SCG0); /* Enable the FLL control loop */

UCSCTL5 |= DIVS__1 | DIVA__32;
UCSCTL4 = SELM__DCOCLK | SELS__DCOCLK | SELA__XT1CLK; /* 24MHz MCLK, 24MHz SMCLK, ACLK (25Mhz/32)*/

__delay_cycles(100);

I tried to add this part of code form the sample program since the crystal was force limited to 8Mhz like mentioned. Having this part of code or not resulted in the same clock result. This was just a blind try from my side!.

Surya Prakash95 said:

PMMCTL0_H = PMMPW_H;
SVSMHCTL&=~SVSMHRRL_7;
SVSMHCTL|=SVSMHRRL_4;
AUX3CHCTL = AUXCHKEY | AUXCHEN | AUXCHC_1 | AUXCHV_1;
AUXCTL0 = AUXKEY;
AUXADCCTL = AUXADC | AUXADCSEL_0 | AUXADCR_0;
AUXCTL2 |=AUX0LVL_6 +AUX1LVL_5 + AUX2LVL_5;
AUXIE |= (AUX0SWIE | AUX1SWIE | AUX2SWIE | AUXSWGIE | AUX0DRPIE | AUX1DRPIE | AUX2DRPIE | AUXMONIE );
PMMCTL0_H = 0;