https://e2e.ti.com/support/microcontrollers/msp-low-power-microcontrollers-group/msp430/Welcome to the MSP Low-Power Microcontrollers Section of the TI E2E Support Community, with support for MSP430™︎ and MSP432™︎ products. Ask questions, share knowledge, explore ideas, and help solve problems with fellow engineers.en-USTelligent Community 13https://e2e.ti.com/support/microcontrollers/msp-low-power-microcontrollers-group/msp430/f/msp-low-power-microcontroller-forum/1642097/msp430g2230-is-a-capacitor-required-on-rst-pin/6335244Wed, 06 May 2026 18:50:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:c9da3803-e494-47a0-9c48-322d3903318eDavid SchultzSee Table 2-3, Connection of Unused Pins, in the guide.https://e2e.ti.com/support/microcontrollers/msp-low-power-microcontrollers-group/msp430/f/msp-low-power-microcontroller-forum/1642097/msp430g2230-is-a-capacitor-required-on-rst-pin/6335167Wed, 06 May 2026 17:42:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:767727d5-50c0-4512-a81b-a43779aa67c3Jerry BucciOwen, Is a 47K pullup also recommended? Is there no internal pullup? Thanks Jerryhttps://e2e.ti.com/support/microcontrollers/msp-low-power-microcontrollers-group/msp430/f/msp-low-power-microcontroller-forum/1643095/msp430fr6047-msp430fr6047-uss-channelsWed, 06 May 2026 13:58:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:0748e572-e54b-4c01-b554-57586d672f54Paolo CostantiniPart Number: MSP430FR6047 Good morning, I have a question related to MSP430FR6047 ultrasonic front-end. I see thath MSP430FR6047 provides 2 USS channels (CH0 and CH1) to connect piezoelectic sensors. Ultrasonic sensor software library (ussSwLib) from TI provides the following different methods to use USS channels: //! \brief This defines the capture sequence selection CH0 #define USS_CAPTURE_SEQUENCE_SELECTION_CH0 --> TX from CH0, RX on CH1 //! \brief This defines the capture sequence selection CH1 #define USS_CAPTURE_SEQUENCE_SELECTION_CH1 --> TX from CH1, RX on CH0 //! \brief This defines the capture sequence selection CH0_CH1 #define USS_CAPTURE_SEQUENCE_SELECTION_CH0_CH1 --> TX from CH0, RX on CH1, then TX from CH1, RX on CH0 and so on for the others: //! \brief This defines the capture sequence selection CH1_CH0 #define USS_CAPTURE_SEQUENCE_SELECTION_CH1_CH0 3 //! \brief This defines the capture sequence selection CH0_CH0 #define USS_CAPTURE_SEQUENCE_SELECTION_CH0_CH0 4 //! \brief This defines the capture sequence selection CH1_CH1 #define USS_CAPTURE_SEQUENCE_SELECTION_CH1_CH1 5 //! \brief This defines the capture sequence selection CH0_CH1_CH0 #define USS_CAPTURE_SEQUENCE_SELECTION_CH0_CH1_CH0 6 //! \brief This defines the capture sequence selection CH1_CH0_CH1 #define USS_CAPTURE_SEQUENCE_SELECTION_CH1_CH0_CH1 7 //! \brief This defines the capture sequence selection CH0_CH0_CH0 #define USS_CAPTURE_SEQUENCE_SELECTION_CH0_CH0_CH0 8 //! \brief This defines the capture sequence selection CH1_CH1_CH1 #define USS_CAPTURE_SEQUENCE_SELECTION_CH1_CH1_CH1 9 //! \brief This defines the capture sequence selection CH0_CH1_CH0_CH1 #define USS_CAPTURE_SEQUENCE_SELECTION_CH0_CH1_CH0_CH1 10 //! \brief This defines the capture sequence selection CH1_CH0_CH1_CH0 #define USS_CAPTURE_SEQUENCE_SELECTION_CH1_CH0_CH1_CH0 11 //! \brief This defines the capture sequence selection CH0_CH0_CH0_CH0 #define USS_CAPTURE_SEQUENCE_SELECTION_CH0_CH0_CH0_CH0 12 //! \brief This defines the capture sequence selection CH1_CH1_CH1_CH1 #define USS_CAPTURE_SEQUENCE_SELECTION_CH1_CH1_CH1_CH1 13 I want to transmit a signal from CH0 and receive an echo signal on the same CH0. Is there a way to allow this scenario? Thanks in advance, Paolo.MSP430FR6047https://e2e.ti.com/support/microcontrollers/msp-low-power-microcontrollers-group/msp430/f/msp-low-power-microcontroller-forum/1641838/mspm0-sdk-sysconfig-issue-in-switching-the-device/6334731Wed, 06 May 2026 13:45:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:4d56bbe8-e18f-4e09-bc7d-293e62158e31Owen LiHi Yesol, What version of SysConfig are you using? Are you on 1.27? Best, Owenhttps://e2e.ti.com/support/microcontrollers/msp-low-power-microcontrollers-group/msp430/f/msp-low-power-microcontroller-forum/1642795/mspm0g3519-noinit-section-with-clang-compiler-and-also-with-ghs-compiler/6334501Wed, 06 May 2026 10:38:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:5b58b47a-f498-41b8-b825-b3402dee201aHelic ChiThe default mode setting is: Mcu_PerformSoftSysReset ((uint32)Reset_Mode); in Mcu.c file And the Reset_Mode is MCU_PERFORM_RESET_MODE_BOOTRST = 1 Which means in the TRM: 2.7.39 RESETLEVEL = 1, And in this reset level, in TRM Table 2-12. Reset Cause Encoding 0x0D 13 Software-triggered BOOTRST These component will be reset: Include SRAM. Choose one reset level that don't trigger SRAM reset. If you entered MSPM0 ROM BSL, a BCR Execution is required, if you use your own bootloader in Flash, CPU reset is enough.https://e2e.ti.com/support/microcontrollers/msp-low-power-microcontrollers-group/msp430/f/msp-low-power-microcontroller-forum/1642795/mspm0g3519-noinit-section-with-clang-compiler-and-also-with-ghs-compiler/6334483Wed, 06 May 2026 10:25:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:d2fc9cc8-798e-4482-8dab-fd8c4fcf50f9Lokesh UpparaHi Chi, We are invoking Mcu_PerformReset() API. UseCase: To verify the transitioning from the Application to Bootloader .https://e2e.ti.com/support/microcontrollers/msp-low-power-microcontrollers-group/msp430/f/msp-low-power-microcontroller-forum/1642997/mspm0g3507-error-cortex_m0p-data-block-size-less-than-1kb-verification-failed-for-datablock-at0x0Wed, 06 May 2026 10:16:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:b9b07382-b940-433e-88d9-8309ff0f9cf9sowmya NPart Number: MSPM0G3507 Other Parts Discussed in Thread: UNIFLASH [ERROR] CORTEX_M0P: Data Block Size less than 1KB!!! Verification Failed for Datablock at0x0 MSPMG3507 Contoller. getting error while updating code from uniflash bootloader. Please guide me how to solve this issue. [5/6/2026, 3:27:10 PM] [INFO] CORTEX_M0P: Programming memory time elapsed: 26.88s[5/6/2026, 3:27:10 PM] [INFO] CORTEX_M0P: Number of bytes programmed: 25520 bytes[5/6/2026, 3:27:10 PM] [INFO] CORTEX_M0P: Programming speed: 0.927kByte/s[5/6/2026, 3:27:10 PM] [ERROR] CORTEX_M0P: Data Block Size less than 1KB!!! Verification Failed for Datablock at0x0[5/6/2026, 3:27:10 PM] [INFO] CORTEX_M0P: CRC check at 0x0 does not match. expected value: 0xF582EB02 obtained from BSL: 0x3A9E479E[5/6/2026, 3:27:10 PM] [INFO] CORTEX_M0P: [80] [09] [00] [26] [00] [00] [00] [00] [C0] [2E] [00] [00] [94] [95] [83] [AC][5/6/2026, 3:27:10 PM] [INFO] CORTEX_M0P: {00}{08} {05} {00} {32} {9E} {47} {9E} {3A} {F0} {90} {B8} {E3}[5/6/2026, 3:27:11 PM] [INFO] CORTEX_M0P: Verifying memory at : 0x2EC0 is match with the expected CRC value: 0x12139349[5/6/2026, 3:27:11 PM] [INFO] CORTEX_M0P: [80] [09] [00] [26] [C0] [2E] [00] [00] [C0] [2E] [00] [00] [62] [90] [A7] [49][5/6/2026, 3:27:11 PM] [INFO] CORTEX_M0P: {00}{08} {05} {00} {32} {49} {93} {13} {12} {C0} {C2} {23} {69}[5/6/2026, 3:27:11 PM] [INFO] CORTEX_M0P: Verifying memory at : 0x5D80 is match with the expected CRC value: 0x5195651F[5/6/2026, 3:27:11 PM] [INFO] CORTEX_M0P: [80] [09] [00] [26] [80] [5D] [00] [00] [30] [06] [00] [00] [C6] [99] [82] [0D][5/6/2026, 3:27:11 PM] [INFO] CORTEX_M0P: {00}{08} {05} {00} {32} {1F} {65} {95} {51} {3B} {B2} {00} {B4}[5/6/2026, 3:27:11 PM] [INFO] CORTEX_M0P: Verifying memory time elapsed: 0.1049s[5/6/2026, 3:27:11 PM] [INFO] CORTEX_M0P: System Reset Issued!!![5/6/2026, 3:27:11 PM] [INFO] CORTEX_M0P: System reset is executed![5/6/2026, 3:27:11 PM] [INFO] CORTEX_M0P: [80] [01] [00] [40] [E2] [51] [21] [5B][5/6/2026, 3:27:11 PM] [SUCCESS] Program Load completed successfully. .cmd file setting -uinterruptVectors --stack_size=512 MEMORY { FLASH (RX) : origin = 0x00000000, length = 0x00020000 SRAM (RWX) : origin = 0x20200000, length = 0x00008000 BCR_CONFIG (R) : origin = 0x41C00000, length = 0x00000080 BSL_CONFIG (R) : origin = 0x41C00100, length = 0x00000080 } SECTIONS { .intvecs: > 0x00000000 .text : palign(8) {} > FLASH .const : palign(8) {} > FLASH .cinit : palign(8) {} > FLASH .pinit : palign(8) {} > FLASH .rodata : palign(8) {} > FLASH .ARM.exidx : palign(8) {} > FLASH .init_array : palign(8) {} > FLASH .binit : palign(8) {} > FLASH .TI.ramfunc : load = FLASH, palign(8), run=SRAM, table(BINIT) .vtable : > SRAM .args : > SRAM .data : > SRAM .bss : > SRAM .sysmem : > SRAM .stack : > SRAM (HIGH) .BCRConfig : {} > BCR_CONFIG .BSLConfig : {} > BSL_CONFIG }UniFlashMSPM0G3507Aerospace & Defensehttps://e2e.ti.com/support/microcontrollers/msp-low-power-microcontrollers-group/msp430/f/msp-low-power-microcontroller-forum/1641832/mspm0g3507-tima-deadband-behavior-when-risedelay-exceeds-pwm-cycle-in-center-aligned-mode/6334388Wed, 06 May 2026 09:20:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:ee1d77cf-ed91-494f-a648-23ee72b91745Helic ChiPlease avoid to use in this way, the mode 1's delay exceed the zero event of Timer will affect the output. Try to use in mode 0 mode, or your software need to check the CC + deadband value before write to register.https://e2e.ti.com/support/microcontrollers/msp-low-power-microcontrollers-group/msp430/f/msp-low-power-microcontroller-forum/1642795/mspm0g3519-noinit-section-with-clang-compiler-and-also-with-ghs-compiler/6334235Wed, 06 May 2026 07:33:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:1e4ac615-865e-4aae-81dc-a8178e896fceHelic ChiWhat level of reset do you performed to reset the device?https://e2e.ti.com/support/microcontrollers/msp-low-power-microcontrollers-group/msp430/f/msp-low-power-microcontroller-forum/1642795/mspm0g3519-noinit-section-with-clang-compiler-and-also-with-ghs-compilerWed, 06 May 2026 01:23:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:c979afc1-102f-4d88-883f-3122d09d3e34Lokesh UpparaPart Number: MSPM0G3519 I am trying to use a NOINIT section, but the structure variable is not retained after a reset. Could you please provide a detailed example of the required linker configuration and C code/memmap file changes for both Clang and GHS compilers? Test Environment : Target : TI(MSPM0G3519) Currently: Compiler : Clang (ticgt) (400_LTS) MCAL : MSPM0-MCAL_0.2.5.0 Planned: Compiler : GHS multi (202414) MCAL : MSPM0-MCAL_00_09.00.00MSPM0G3519https://e2e.ti.com/support/microcontrollers/msp-low-power-microcontrollers-group/msp430/f/msp-low-power-microcontroller-forum/1642739/mspm0l1306-temperature-sensor-example-code/6333658Tue, 05 May 2026 20:31:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:c9a513d5-e0ee-4815-842f-6036735d56a0Owen LiHi Lucy, There is an example titled adc12_internal_temp_sensor_mathacl for the MSPM0G3507 and MSPM0G3519 family devices. You can reference these examples to implement an example that does not use the IQ Math library. Furthermore, Chapter 14 in the Technical Reference Manual provides information and examples for using the temperature sensor. Best, Owenhttps://e2e.ti.com/support/microcontrollers/msp-low-power-microcontrollers-group/msp430/f/msp-low-power-microcontroller-forum/1640132/mspm0g3519-mspm0g3519-80-mhz-configuartion-example-code-causing-device-mismatch-issue/6333638Tue, 05 May 2026 20:08:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:ac40e92a-a7ef-4cf9-8640-0c12df2ec68cDiego Abad SajaminHi Paul, Please try both examples provided here, and let me know what is are the results. I am not able to replicate the issue from my setup. e2e.ti.com/.../sysctl_5F00_mclk_5F00_syspll_5F00_LP_5F00_MSPM0G3519_5F00_nortos_5F00_ticlang.zip e2e.ti.com/.../MSPM0G3519_5F00_SYSPLL.zip Best Regards, Diego Abadhttps://e2e.ti.com/support/microcontrollers/msp-low-power-microcontrollers-group/msp430/f/msp-low-power-microcontroller-forum/1642739/mspm0l1306-temperature-sensor-example-codeTue, 05 May 2026 19:05:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:efc8b343-1f9d-4579-9ab7-64f92771ee8eLucy Fanelli76Part Number: MSPM0L1306 Other Parts Discussed in Thread: MSPM0G3507 , MSPM0G3519 Hello, Is there any example code (using code composer studio) for reading the internal temperature sensor in this device? I didn't see any in the examples list, and I'm wondering how to configure the ADC and reference, and how to calculate an actual temperature from the result using the internal factory constants. Thanks, LucyMSPM0L1306MSPM0G3507MSPM0G3519Aerospace & Defensehttps://e2e.ti.com/support/microcontrollers/msp-low-power-microcontrollers-group/msp430/f/msp-low-power-microcontroller-forum/1641827/msp432e401y-j-link-to-set-mac-address/6333184Tue, 05 May 2026 14:02:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:0e323e17-a9ba-40fc-ade0-0e15a0ccda7bBruce McKenneyYou can write to USER_REG0/1 at 0x400FE1E0/4, but the values won't persist (over a Reset) until they have been "Commit"ted. The Commit procedure is described in TRM (SLAU723A) Sec 7.2.3.12 and illustrated in the Driverlib function FlashUserSave(). I imagine this could be done in a JLink script, though I haven't had occasion to script a busy-wait (loop). I don't see a .gel procedure to do this. The debugger (Tools->On-Chip Flash->MAC Address) can do this, but it's a manual process. [Edit: Keep in mind that once you do this Commit, you need to do a Factory Reset before you can do it again.]https://e2e.ti.com/support/microcontrollers/msp-low-power-microcontrollers-group/msp430/f/msp-low-power-microcontroller-forum/1641827/msp432e401y-j-link-to-set-mac-address/6333159Tue, 05 May 2026 13:40:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:e7a4d99b-b3f6-4966-8338-7c58c1c57fc2Eric RentschlerHi Catherine, Looks like the USEREGs start at 0x400FE1E0. Thanks, -Eric Rentschlerhttps://e2e.ti.com/support/microcontrollers/msp-low-power-microcontrollers-group/msp430/f/msp-low-power-microcontroller-forum/1642551/mspm0g3519-fee-initialization-issue-with-ghs-compiler/6333115Tue, 05 May 2026 12:48:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:bc23536f-90d8-42ea-a4b7-620668959e7dSreekar SreekarHi, Please add the below code into the suggested files as follows: In linker command file of GHS, add a section .eraseLoadSram align(16) : { __ghsbegin_eraseLoadSram = .; *(.eraseLoadSram) . = ALIGN(16); __ghsend_eraseLoadSram = .; } > FLASH In Fls_ac.h, add/check this section #elif defined(__ghs__) || defined(GHS) /* GHS compiler: Use #pragma ghs section for section placement */ #pragma ghs section text=".eraseLoadSram" void Fls_executeCommand(void); #pragma ghs section text=default In Fls_ac.c, add/check this section #if defined(__ghs__) || defined(GHS) /* GHS compiler: Use #pragma ghs section to place function in .eraseLoadSram */ #pragma ghs section text=".eraseLoadSram" #endif In Fls_ctrl.c, add/check this section #elif defined(__ghs__) || defined(GHS) /* GHS compiler: Use linker-defined symbols for section info */ /* These symbols should be defined in the linker script */ extern uint32 __ghsbegin_eraseLoadSram[]; extern uint32 __ghsend_eraseLoadSram[]; #define eraseLoadFlashStart __ghsbegin_eraseLoadSram #define eraseLoadFlashSize ((uint32)((uint8*)__ghsend_eraseLoadSram - (uint8*)__ghsbegin_eraseLoadSram)) This will ensure that the Fls_executeCommand() API is correctly copied from flash to sram and executed from sram. Thanks, Sreekarhttps://e2e.ti.com/support/microcontrollers/msp-low-power-microcontrollers-group/msp430/f/msp-low-power-microcontroller-forum/1641827/msp432e401y-j-link-to-set-mac-address/6332917Tue, 05 May 2026 08:50:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:c447da8e-9113-48ab-a04a-113bce0a219eCatherine BrownHi, Thanks, that explanation makes sense. However, it’s not quite what I’m trying to achieve, I am looking for a way to set the MAC address after I've programmed the bootloader in J-Link. Is there a way to do that? Is there a particular address for the USERREGs that I can write to via J-Link.exe.https://e2e.ti.com/support/microcontrollers/msp-low-power-microcontrollers-group/msp430/f/msp-low-power-microcontroller-forum/1642551/mspm0g3519-fee-initialization-issue-with-ghs-compilerTue, 05 May 2026 08:36:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:704e3b5c-55c1-48e3-bd14-c6d70a3669e8Veeresh KariyappaPart Number: MSPM0G3519 Issue Description: While performing Fee_Init() using latest MCAL package from TI. Below are the observations. Fee module invokes Fls_blankVerifyFlashWord() as shown below During the execution of funcRun(), it is observed that OS Exception is reported. Rootcause Analysis: Fls user guide mentions to have linker command file(CLANG Compiler) as shown below When Clang compiler is used for building Application, we have not observed Fee initialization issue, but when GHS compiler is used, the issue is observed. Linker script for GHS compiler : Generated .map Is MCAL verified with GHS compiler at TI for Fee initialization? and Can you please share the linker command file used for the initialization of Fee with GHS compiler ? Test Environment : Target : TI(MSPM0G3519) Compiler : GHS multi (202414) MCAL : MSPM0-MCAL_00_09.00.00 Please let me know if any information is required.MSPM0G3519https://e2e.ti.com/support/microcontrollers/msp-low-power-microcontrollers-group/msp430/f/msp-low-power-microcontroller-forum/1597657/msp430fr2676-gang-with-external-power-supply/6332607Tue, 05 May 2026 02:14:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:68012bc0-33b4-4cf3-a48f-215fa04b5083Brian LeeHi Ryuuichi, There has unfortunately been another stall in this. I do not have a firm date, but expect to have more updates on this matter later this week. Best Regards, Brianhttps://e2e.ti.com/support/microcontrollers/msp-low-power-microcontrollers-group/msp430/f/msp-low-power-microcontroller-forum/1640132/mspm0g3519-mspm0g3519-80-mhz-configuartion-example-code-causing-device-mismatch-issue/6332576Tue, 05 May 2026 00:33:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:94ab4827-91fc-4132-8c64-293883a6b835Diego Abad SajaminHi Paul, That's weird. Let me try to replicate the issue and create a custom code you can use to test. Best Regards, Diego Abad