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Interfacing of MSP430f5438 with ADS8507 (16 bit ADC) and programming

kush tripathi
Prodigy 35 points
Other Parts Discussed in Thread: MSP430F5438, ADS8507

Dear all,

I am very new to programming MSP430, I have been given a task to interface MSP430f5438 with an external 16 bit SAR ADC (ADS8507). Please help me in the coding for the above case.
I am using Olimex (MSP430f5438stk) as a development module.

Any kind of suggestion and help will be appreciated 

  • 0
    Guru 227245 points

    The ADS has an SPI compatible interface.

    How to program SPI is explained in the family users guide. The MSP430F5438 has four USCI modeuls with up to 8 independent SPI channels. Which one to use depends on how you want to connect the ADS toteh experimenters board. See the board schematics for a suitable connection.

    You'll need a SOMI and SCLK line (called SDATA and DATACLK in the ADS datasheet), as well as soem standard I/O pins.

    One I/O signal is required for the CS signal. If high, the ADS will be inactive. Normally, the CS signal is used to select one of a series of parallel connected SPI slaves. All whose CS signal is high won't respond to the masters clock signal and ignore the masters data output. If the ADS is the only SPi device on the bus, you may as well fix the CS pin to GND.

    Second signal you need is the R/C signal. When it is set to low, a new conversion will start. It must be low for at least 40ns and at most 12µs.

    Third signal you need is either the ext/int or the busy signal as an input. Wile either one of them is low, you can receive data from the last (!) conversion by writing two bytes to TXBUF (which in turn will receive two bytes in RXBUF: the conversion result).

    If using BUSY, while BUSY is high, you can read the result of the last conversion, When you start a new conversion, BUSY goes low, but you can still read the result form the last conversion. However, the transfer must be finished before BUSY goes (will go?) high again and a new transfer can be started. Also, between BUSY going high and start of a data read (of just finished conversion), or between R/C going high again (start of  anew conversion) and the begin of a read of the result of the previous converison, certain minimum delays are required.

    See ADS datasheet, Table3 and fig 37-39.

    About SPI master programming on teh USCI, there are several threads on this forum.

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