Hello,
I'm having problem getting these to communicate. I'm using the TI example code for both these parts at 9600 baud rate, the G2153 is sending and the F149 is receiving. I've checked that the right pins are connected as well as ground. I also tried using the G2153 with a F5438 and that worked fine, so I'm not sure why the F149 is not. I attached the code for both. Thanks.
8867.fet140_uart01_09600.c
//******************************************************************************
// MSP-FET430P140 Demo - USART0, UART 9600 Echo ISR, HF XTAL ACLK
//
// Description: Echo a received character, RX ISR used. Normal mode is LPM0,
// USART0 RX interrupt triggers TX Echo. Though not required, MCLK = LFXT1
// ACLK = MCLK = UCLK0 = LFXT1 = 3.58MHz
// Baud rate divider with 3.58Mhz XTAL @9600 = 3.58MHz/9600 = 372 (0174h)
// //* An external 3.58Mhz XTAL on XIN XOUT is required for ACLK *//
//
// MSP430F149
// -----------------
// /|\| XIN|-
// | | | 3.58MHz
// --|RST XOUT|-
// | |
// | P3.4|------------>
// | | 9600 - 8N1
// | P3.5|<------------
//
//
// M. Buccini
// Texas Instruments Inc.
// Feb 2005
// Built with CCE Version: 3.2.0 and IAR Embedded Workbench Version: 3.21A
//******************************************************************************
#include <msp430x14x.h>
void main(void)
{
volatile unsigned int i;
WDTCTL = WDTPW + WDTHOLD; // Stop WDT
P3SEL |= 0x30; // P3.4,5 = USART0 TXD/RXD
BCSCTL1 |= XTS; // ACLK = LFXT1 = HF XTAL
do
{
IFG1 &= ~OFIFG; // Clear OSCFault flag
for (i = 0xFF; i > 0; i--); // Time for flag to set
}
while ((IFG1 & OFIFG)); // OSCFault flag still set?
BCSCTL2 |= SELM_3; // MCLK = LFXT1 (safe)
ME1 |= UTXE0 + URXE0; // Enable USART0 TXD/RXD
UCTL0 |= CHAR; // 8-bit character
UTCTL0 |= SSEL0; // UCLK = ACLK
UBR00 = 0x74; // 3.58Mhz/9600 - 372
UBR10 = 0x01; //
UMCTL0 = 0x00; // no modulation
UCTL0 &= ~SWRST; // Initialize USART state machine
IE1 |= URXIE0; // Enable USART0 RX interrupt
_BIS_SR(LPM0_bits + GIE); // Enter LPM0 w/ interrupt
}
#pragma vector=USART0RX_VECTOR
__interrupt void usart0_rx (void)
{
while (!(IFG1 & UTXIFG0)); // USART0 TX buffer ready?
TXBUF0 = RXBUF0; // RXBUF0 to TXBUF0
}
8322.test.c
//******************************************************************************
// MSP430G2xx3 Demo - USCI_A0, SPI 3-Wire Slave Data Echo
//
// Description: SPI slave talks to SPI master using 3-wire mode. Data received
// from master is echoed back. USCI RX ISR is used to handle communication,
// CPU normally in LPM4. Prior to initial data exchange, master pulses
// slaves RST for complete reset.
// ACLK = n/a, MCLK = SMCLK = DCO ~1.2MHz
//
// Use with SPI Master Incremented Data code example. If the slave is in
// debug mode, the reset signal from the master will conflict with slave's
// JTAG; to work around, use IAR's "Release JTAG on Go" on slave device. If
// breakpoints are set in slave RX ISR, master must stopped also to avoid
// overrunning slave RXBUF.
//
// MSP430G2xx3
// -----------------
// /|\| XIN|-
// | | |
// | | XOUT|-
// Master---+-|RST |
// | P1.2|<- Data Out (UCA0SOMI)
// | |
// | P1.1|-> Data In (UCA0SIMO)
// | |
// | P1.4|<- Serial Clock In (UCA0CLK)
//
// D. Dang
// Texas Instruments Inc.
// February 2011
// Built with CCS Version 4.2.0 and IAR Embedded Workbench Version: 5.10
//******************************************************************************
#include "msp430g2553.h"
char tmp;
void main(void)
{
WDTCTL = WDTPW + WDTHOLD; // Stop watchdog timer
while (!(P1IN & BIT5)); // If clock sig from mstr stays low,
// it is not yet in SPI mode
P1SEL |= BIT7 + BIT5;
P1SEL2 |= BIT7 + BIT5;
UCB0CTL1 = UCSWRST; // **Put state machine in reset**
UCB0CTL0 |= UCCKPL + UCMSB + UCSYNC; // 3-pin, 8-bit SPI master
UCB0CTL1 &= ~UCSWRST; // **Initialize USCI state machine**
IE2 |= UCB0RXIE; // Enable USCI0 RX interrupt
BCSCTL1 = CALBC1_1MHZ; // Set DCO
DCOCTL = CALDCO_1MHZ;
P1SEL |= BIT1 + BIT2 ; // P1.1 = RXD, P1.2=TXD
P1SEL2 |= BIT1 + BIT2 ; // P1.1 = RXD, P1.2=TXD
UCA0CTL1 |= UCSSEL_2; // SMCLK
UCA0BR0 = 104; // 1MHz 9600
UCA0BR1 = 0; // 1MHz 9600
UCA0MCTL = UCBRS0; // Modulation UCBRSx = 1
UCA0CTL1 &= ~UCSWRST; // **Initialize USCI state machine**
IE2 |= UCA0RXIE; // Enable USCI_A0 RX interrupt
__bis_SR_register(LPM0_bits + GIE);
}
// Echo character
#pragma vector=USCIAB0RX_VECTOR
__interrupt void USCI0RX_ISR (void)
{
while (!(IFG2 & UCA0TXIFG)); // USCI_A0 TX buffer ready?
UCA0TXBUF = UCB0RXBUF;
}
