Hi,
I am trying to send data through SPI from MSP430F2370 to MSP430G2153, I am using the example code from TI but the receiver isn't getting the same data that is transmitted. I only need to send data so I just have the SIMO and CLK lines connected. Do I need a SS if it is just the 2 MCUs? For example I send 0x58, but I receive 0x61.
Here's the code for both:
2768.8322.c
//******************************************************************************
// MSP430G2xx3 Demo - USCI_A0, SPI 3-Wire Slave Data Echo
//
// Description: SPI slave talks to SPI master using 3-wire mode. Data received
// from master is echoed back. USCI RX ISR is used to handle communication,
// CPU normally in LPM4. Prior to initial data exchange, master pulses
// slaves RST for complete reset.
// ACLK = n/a, MCLK = SMCLK = DCO ~1.2MHz
//
// Use with SPI Master Incremented Data code example. If the slave is in
// debug mode, the reset signal from the master will conflict with slave's
// JTAG; to work around, use IAR's "Release JTAG on Go" on slave device. If
// breakpoints are set in slave RX ISR, master must stopped also to avoid
// overrunning slave RXBUF.
//
// MSP430G2xx3
// -----------------
// /|\| XIN|-
// | | |
// | | XOUT|-
// Master---+-|RST |
// | P1.2|<- Data Out (UCA0SOMI)
// | |
// | P1.1|-> Data In (UCA0SIMO)
// | |
// | P1.4|<- Serial Clock In (UCA0CLK)
//
// D. Dang
// Texas Instruments Inc.
// February 2011
// Built with CCS Version 4.2.0 and IAR Embedded Workbench Version: 5.10
//******************************************************************************
#include "msp430g2153.h"
char tmp;
void main(void)
{
WDTCTL = WDTPW + WDTHOLD; // Stop watchdog timer
while (!(P1IN & BIT5)); // If clock sig from mstr stays low,
// it is not yet in SPI mode
P1OUT |= BIT4;
P1SEL |= BIT7 + BIT5;
P1SEL2 |= BIT7 + BIT5;
UCB0CTL1 = UCSWRST; // **Put state machine in reset**
UCB0CTL0 |= UCCKPL + UCMSB + UCSYNC; // 3-pin, 8-bit SPI master
UCB0CTL1 &= ~UCSWRST; // **Initialize USCI state machine**
IE2 |= UCB0RXIE; // Enable USCI0 RX interrupt
// UCB0TXBUF = 0x00;
BCSCTL1 = CALBC1_1MHZ; // Set DCO
DCOCTL = CALDCO_1MHZ;
P1SEL |= BIT1 + BIT2 ; // P1.1 = RXD, P1.2=TXD
P1SEL2 |= BIT1 + BIT2 ; // P1.1 = RXD, P1.2=TXD
UCA0CTL1 |= UCSSEL_2; // SMCLK
UCA0BR0 = 104; // 1MHz 9600
UCA0BR1 = 0; // 1MHz 9600
UCA0MCTL = UCBRS0; // Modulation UCBRSx = 1
UCA0CTL1 &= ~UCSWRST; // **Initialize USCI state machine**
IE2 |= UCA0RXIE; // Enable USCI_A0 RX interrupt
__bis_SR_register(LPM0_bits + GIE);
}
// Echo character
#pragma vector=USCIAB0RX_VECTOR
__interrupt void USCI0RX_ISR (void)
{
// tmp = UCB0RXBUF;
while (!(IFG2 & UCA0TXIFG)); // USCI_A0 TX buffer ready?
UCA0TXBUF = UCB0RXBUF;
}
3603.msp430x23x0_uscia0_spi_09.c
//******************************************************************************
// MSP430F23x0 Demo - USCI_A0, SPI 3-Wire Master Incremented Data
//
// Description: SPI master talks to SPI slave using 3-wire mode. Incrementing
// data is sent by the master starting at 0x01. Received data is expected to
// be same as the previous transmission. USCI RX ISR is used to handle
// communication with the CPU, normally in LPM0. If high, P1.0 indicates
// valid data reception.
// ACLK = n/a, MCLK = SMCLK = DCO ~1.2MHz, BRCLK = SMCLK/2
//
// Use with SPI Slave Data Echo code example. If slave is in debug mode, P3.6
// slave reset signal conflicts with slave's JTAG; to work around, use IAR's
// "Release JTAG on Go" on slave device. If breakpoints are set in
// slave RX ISR, master must stopped also to avoid overrunning slave
// RXBUF.
//
// MSP430F23x0
// -----------------
// /|\| XIN|-
// | | |
// --|RST XOUT|-
// | |
// | P3.4|-> Data Out (UCA0SIMO)
// | |
// LED <-|P1.0 P3.5|<- Data In (UCA0SOMI)
// | |
// Slave reset <-|P3.6 P3.0|-> Serial Clock Out (UCA0CLK)
//
//
// A. Dannenberg
// Texas Instruments Inc.
// January 2007
// Built with CCE Version: 3.2.0 and IAR Embedded Workbench Version: 3.41A
//******************************************************************************
#include "msp430x23x0.h"
unsigned char MST_Data, SLV_Data;
void main(void)
{
volatile unsigned int i;
WDTCTL = WDTPW + WDTHOLD; // Stop watchdog timer
P1OUT = 0x00; // P1 setup for LED
P1DIR |= 0x01; //
// P3OUT = BIT3; // Set slave reset
// P3DIR |= BIT3; //
P3SEL |= BIT1 + BIT2 + BIT3; // P3.0,4,5 USCI_A0 option select
UCB0CTL0 |= UCCKPL + UCMSB + UCMST + UCSYNC; // 3-pin, 8-bit SPI master
UCB0CTL1 |= UCSSEL_2; // SMCLK
UCB0BR0 |= 0x02; // /2
UCB0BR1 = 0; //
// UCB0MCTL = 0; // No modulation
UCB0CTL1 &= ~UCSWRST; // **Initialize USCI state machine**
IE2 |= UCB0RXIE; // Enable USCI0 RX interrupt
// P3OUT &= ~BIT3; // Now with SPI signals initialized,
// P3OUT |= BIT3; // reset slave
// for (i = 50; i > 0; i--); // Wait for slave to initialize
MST_Data = 0x50; // Initialize data values
SLV_Data = 0x00;
UCB0TXBUF = MST_Data; // Transmit first character
UCB0TXBUF = 0x20;
UCB0TXBUF= 0x30;
UCB0TXBUF= 0x40;
while (1)
{
UCB0TXBUF= 0xFF;
}
__bis_SR_register(LPM0_bits + GIE); // CPU off, enable interrupts
}
// Test for valid RX and TX character
#pragma vector=USCIAB0RX_VECTOR
__interrupt void USCIB0RX_ISR(void)
{
volatile unsigned int i;
while (!(IFG2 & UCB0TXIFG)); // USCI_A0 TX buffer ready?
UCB0TXBUF = MST_Data; // Send next value
for (i = 30; i; i--); // Add time between transmissions to
} // make sure slave can keep up
Thanks for your help.
