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SPI Modes 0 and MOde 3

SRIHK
Intellectual 975 points
Other Parts Discussed in Thread: MSP430F148

Hi,

    Im using MSP430F148 and trying to interface AT45DB321C but little confused about the Modes 0 and mode 3 because the document SLAU049 dosent mention clearly about the modes ,

      well I am thinking that           U1TCTL = CKPL + SSEL1 + STC;              // Polarity, SMCLK, 3-wire, selected  mode 3

    selects mode 3 because for Mode 3 CKPL=1,CKPH=0 is it correct please help me if Im wrong ,Thnx in advance

  • 0
    Prodigy 245 points

    Hi,

    Ya that looks fine to me. If you look at Page 14-10 on SLAY049 you'll see a timing diagram that makes it easy to see what value of CKPH and CKPL to set.

    Dave

  • 0 in reply to Dave14551
    Intellectual 975 points

    Hi,

         I've seen that page 14-10 from Slau049 but which one do u think is mode 3 and mode 0 please write down in the combinations as CKPH== X and CKPL ==X   for mode X,......

  • 0 in reply to SRIHK
    Prodigy 245 points

    Hi,

    As far as I can see from the timing diagram on page 14-10 of slau049:

    Mode 0 => CKPH = 1, CKPL = 0

    Mode 1 => CKPH = 0, CKPL = 0

    Mode 2 => CKPH = 1, CKPL = 1

    Mode 3 => CKPH = 0, CKPL = 1

    Dave

  • 0 in reply to Dave14551
    Intellectual 645 points

    spi odes are as follows (cpol is the high order bit and the default value f the clock) and depending of the settig of cpol also determines the defnition od what chpa menas (in mode 0 data is read on the risng edge, in mode 2 data is read n the falling edge), this is why many devices work n both modes 0,3 by invertig the phase for an inverted clock, data is now read in both modes n the rising edge and changed on the falling edge just a a different tme from the falling of the CS pin..

    mode cpol cpha

    0    0    0

    1    0     1

    2    1     0

    3    1     1

     

     theway TI lays out the SPI regsters it iplies that cpha is the hgh order bit, but the spi standard naming has cpol as the high order bit.

    here is a short explanation I found tday (09/03) with some diagrams and references

    http://www.totalphase.com/support/kb/10045/

     

     

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