NEED HELP CC430F6137

CAN ANYONE CHANGE THIS CODE TO CC430F6137 

THIS CODE IS WRITTEN IN MSP430F123

I AM GETTING ERROR AT DCO

void sys_init(void)
{
// Configure P1.0,1,2,3 to generate an
// interrupt on high-to-low signal
// transition
P1IES = 0x0f;
P1IFG = 0x00;
P1IE = 0x0f;

// Clear P2 outputs
// Clear P3 outputs
// Configure P2.3,2,1,0 as outputs
// Configure P3.3,2,1,0 as outputs
P2OUT = 0x00;
P3OUT = 0x00;
P2DIR |= 0x0f;
P3DIR |= 0x0f;

// Set DCO frequency
Set_DCO(DCO_FREQ);

// Initialize Timer A
timerA_Init();

// Initialize UART0
uart0_Init();

// Initialize WDT
wdt_Init();
}
//
// Set DCO frequency
//
void Set_DCO(unsigned long freq)
{
unsigned int clkCnt;
unsigned int numDcoClks;
unsigned int prevCnt = 0;

// PUC value for DCOx = 3
// PUC value for RSELx = 4

// Basic Clock system Control Register 1 p. 4-15
BCSCTL1 |= DIVA_3; // ACLK = LFXT1CLK/8 = 4096 Hz

numDcoClks = freq/4096; // Number of DCO clocks in one
// ACLK/8 period

// Timer A Capture/Compare Control Register p. 11-22
TACCTL2 = CM_1 + CCIS_1 + CAP; // Capture on rising Edge
// Capture input is CCI2B = ACLK
// Async capture
// Capture mode
// Output mode is OUT bit
// Interrupt disabled
// OUT bit is 0
// Clear capture overflow bit (COV)
// Clear interrupt pending flag (CCIFG)

// Timer A Control Register p. 11-20
TACTL = TASSEL_2 + MC_2 + TACLR; // Timer A clock source is SMCLK
// Input clock divider is 1,
// Continuous mode (counts up to 0xffff)
// Reset TAR, TACLK divider, and count direction
// Interrupt is disabled
// Clear interrupt pending flag (TAIFG)

while(1)
{
while( !(TACCTL2 & CCIFG) )
{
// Wait for capture event
}

TACCTL2 &= ~CCIFG; // Capture occured, clear flag

clkCnt = TACCR2 - prevCnt; // Number of clocks since last capture

prevCnt = TACCR2; // Save current clock count

if( numDcoClks == clkCnt )
{
break; // If equal, leave "while(1)"
}
else if( clkCnt > numDcoClks ) // DCO is too fast, slow it down
{
DCOCTL--;

if( DCOCTL == 0xFF )
{
if( BCSCTL1 & 0x07 )
{
BCSCTL1--; // DCO role under?, dec RSEL
}
else
{
break; // Error condition, break loop
}
}
}
else // DCO is too slow, speed it up
{
DCOCTL++;

if( DCOCTL == 0x00 )
{
if( (BCSCTL1 & 0x07) != 0x07 )
{
BCSCTL1++; // DCO role over? higher RSEL
}
else
{
break; // Error condition, break loop
}
}
}
}

BCSCTL1 &= ~DIVA_3; // ACLK = LFXT1CLK/1 = 32768 Hz

TACCTL2 = 0; // Stop TACCR2
TACTL = 0; // Stop Timer_A
}
//
// WDT Initialization
//