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msp430g2152 timer A output problem

Henry Lehmann
Prodigy 170 points

All,

I am trying to track down the cause of some odd behavior that I have observed on said processor's timer outputs.  All of the tests were done with Timer A running at 1MHz straight from SMCLK.  The goal is to generate a 1us pulse every 25us.  If I use output mode 7 and set TA0CCR2 to 0x0000h, I get nothing on the output.  If I set TA0CCR2 to 0x0001h, I get a 1us pulse just like I wanted.  Based on the description in the manual, I thought that setting TA0CCR2 to zero would've give me the single pulse, but it does not.  I am curious what I am misunderstanding that causes this to be the case.

Also, one of my coworkers tried it a different way, using mode 3.  They used TA0CCR0=0x0018h, and TA0CCR2=0x0017h.  This gave a 2us pulse at 25us intervals, instead of the 1us we expected to get.  Setting the two registers equal yielded a 1us pulse, but seems counter-intuitive.

Any insight on why we are observing this behavior would be appreciated.

  • 0
    Guru 58965 points

    The User's Guide has all the details. (slau144i.pdf)

  • 0 in reply to old_cow_yellow
    Prodigy 170 points

    This description:

    "The output is set when the timer counts to the TACCRx value. It is reset when the timer counts to the TACCR0 value."

    Does not match mode 3's behavior.  I have figured out why it doesn't, because the reset event does not happen when the timer counts to TACCR0, but rather the transition from TACCR0 to zero, or vise-versa.

  • 0
    Guru 227245 points

    In up mode, the timer behaves apparently different from what the users guide tells. The second trigger point is not the moment TAR counts to CCR0 but ratehr when it rolls over to 0. It makes some sense: Setting CCR0 to 99, gives 0 to 100% DC when setting CCRx to 0..100. It also gives (in opposiiton to the users guide's telling) a peak of 1 tick when you use OUTMOD 2,3,6 or 7 on CCR0.

    The 3x family users guide talks about an additional signal EQU0,delayed, which is used in up mode only instead of EQU0. In all other users guides, only EQU0 (which is set when TAR->CCR0) is mentioned. Since the delayed EQU0 matches your (and my) observations, it is apparently valid for all other families too.

    "EQU0 delayed is used in up mode, not EQU0. EQU0 is active high when TAR = CCR0. EQU0 delayed is active high when TAR = 0."

    Unfortunately, the graphical resolution of the diagrams in the users guide is by far not high enough to see whether an interrupt happens at the beginning or the end of the (in theory almost, but in fact exactly) vertical line from TAR=CCR0 to TAR=0,

    Henry Lehmann said:
     If I use output mode 7 and set TA0CCR2 to 0x0000h, I get nothing

    Setting the output happens when the timer counts to TA0CCR2, and clearing it when it rolls over to 0.
    Since TA0CCR2 is 0, set and reset happen at the same time and one of them always wins.

    Henry Lehmann said:
    They used TA0CCR0=0x0018h, and TA0CCR2=0x0017h.  This gave a 2us pulse at 25us intervals, instead of the 1us we expected to get.

    The timer doesn't immediately roll over to 0 when it reaches the CCR0 value. It doe sso on the next tick.

    So the total period is CCR0+1 ticks. So the set comes when the timer reaches 0x17, and the reset comes when the timer rolls over to 0, two(!) ticks later. The sequence is 16->17->18->0

  • 0 in reply to Jens-Michael Gross
    Prodigy 170 points

    What clued me in was looking very closely at Figure 12-3 and Figure 12-12 in the user's manual.  Note where TAIFG is set in 12-3, and where EQU0+TAIFG are located in 12-12.  The information is there, but as you've also seen its not made very clear in the text descriptions.  In any case, I'm glad its not a bug.

    Thanks all!

  • 0 in reply to Henry Lehmann
    Guru 227245 points

    Figure 12-3 only refers to the TACCR0 and TAIFG interrupt. So it doesn't help here.

    The problem is that in cont or up/down mode, the output changes happen when TAR counts to either CCRx or to CCR0.
    But in up mode (and only in up mode), the second trigger is not CCR0 but the following count to 0.

    The truth is only told here:

    "12.2.5.2 Output Example — Timer in Up Mode
    The OUTx signal is changed when the timer counts up to the TACCRx value, and rolls from TACCR0 to zero, depending on the output mode."

    Even the table right above this sentence doesn't reflect the different behaviour in up mode.

    Also, at many other places, one could get the impression that reaching CCR0 in up mode causes an immediate (asynchronous!) transition to 0, so the CCR0 value never appears in TAR. But instead, TAR rolls over to 0 with the next cycle. (this is why the cycle length is CCR0+1 ticks)

  • 0 in reply to Jens-Michael Gross
    Prodigy 170 points

    Thank you for mentioning the bit about continuous and up/down mode.  We were concerned that this affected those as well.

    We appreciate the information that you have provided, and will keep it in mind going forward.

    -Henry

  • 0 in reply to Henry Lehmann
    Guru 227245 points

    Henry Lehmann said:
    Thank you for mentioning the bit about continuous and up/down mode.  We were concerned that this affected those as well.

    IMHO, the way up mode works is the most natural one. A PWM cycle (which is what up mode was designed for), a pulse begins at zero (and not at CCR0) and ends at the given DC position (CCRx). This is the natural way, and the MSP timer works this way.

    Personally, I think that CCR0 is the wrong trigger in cont and up/down mode too. For up/down mode, 0 and CCR0, as beeing symmetrical endpoints, are exchangeable. And in cont mode, 0 could as well serve as 'endpoint' instead of CCR0 - just a different offset then. And CCR0 could be used as well then in double-action modes.

    Well, the users guide really requires some cleanup here. Until then, I reserved a subchapter in my book for it :)

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