How MSP430F2011 Generating 38KHz 30% Duty Cycle PWM Waveform in low power mode
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How MSP430F2011 Generating 38KHz 30% Duty Cycle PWM Waveform in low power mode
Hold the Watchdog. Set up the DCO to 1MHz if the the calibration constants are still valid. Set up P1.2, P1.6, or P2.6 (your choice) as TimerA2 TA1 output. Set up all unused and not connected GPIO pins as output low. Set up TACCR0 to 30, TACCR1 to 9, TACCTR1 to OUTMOD_7, and TACTL to TASSEL_2 | MC_1. Set SR with CPUOFF | OSCOFF | GIE. Forget about "Low Power Modes"
#include <msp430x20x1.h>
void main(void)
{
WDTCTL = WDTPW +WDTHOLD; // Stop WDT
BCSCTL1 = CALBC1_1MHZ; //SMCLK 1MHZ
DCOCTL=CALDCO_1MHZ;
TACTL=TASSEL1+MC0+ID_2;
P1DIR|=0x01; //P1.0 out
if(BIT1==0)
P1OUT=1;
TACTL|=TAIE; //TA interrupt Ena××e
if(BIT3==0)
P1OUT=0;
TACTL|=TAIE; //TA interrupt Ena××e
if(BIT1+BIT3==0)
_NOP();
else
_NOP();
for (;;)
{
_BIS_SR(LPM2_bits); // Enter LPM2
_NOP(); // Required only for C-spy
}
}
#pragma vector=TIMERA1_VECTOR
__interrupt void Timer_A(void)
{
P1OUT^=0x01;
}
Details are found in the 2x family users guide, timer chapter and clock system chapter.
The PWM generation continues in LPM as long as the clock source for the timer isn’t stopped. (so don’t enter LPM3/LPM4 when the timer is clocked by SMCLK/ACLK and don’t use an LPM>0 if the clock is derived from DCO)
What OCY wants to express in his unrivaled way is that BIT1 is a constant (0x02) and it makes no sense comparing a constant (that is non-zero) to zero. The result will always be false.
The question is: BIT1 of what is to be tested? E.g. “if((P1IN & BIT1)==0)” for BIT1 of P1IN (well, this also can be shortened to “if(!(P1IN&BIT1))” ).
For almost all registers except the port registers, using the BITx defines makes not much sense anyway. Because for their individual control bits individual defines exist (like “CCIFG” for TAxCCRy, Bit 0). Using them makes code much more readable. However, they are still constants.
Is it always gone be 30%?, then it's not PWM (as -Width Modified- part is not used)
Can 50% duty be used?, if so use a 38k crystal instead of a 32.768k and turn on the ACLK output pin on p1.0.
Need 1/3 pulse?
Use cap and resistor and Schmitt trigger buffer to shorten the duration to ~30% probably could be done.
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