Problem configuring DCO clock on MSP430F6720

Hi folks,

I am having some problem configuring DCOCLK as source of MCLK, I wish someone may lend me some help. The plan is to set DCO clock at 16MHz, DCOCLKDIV at 4MHz, then  source MCLK from DCOCLK. I understand this can be easily done by changing:

UCSCTL4 |= SELM__DCOCLK;

But somehow this configuration seems not taking effect. MCLK remains on from DCOCLKDIV as determined by the flashing rate an LED output. The following is my entire code:

int main(void) {
    WDTCTL = WDTPW | WDTHOLD; // Stop watchdog timer

    //Turn on XT1 watch crystal, wait till XT1 stabilize
    UCSCTL6 &= ~(XT1OFF);                   // XT1 On
    UCSCTL6 |= XCAP_3;                      // Internal load cap

    P4SEL &= BIT6;
    P4DIR |= BIT6;
    P4OUT |= BIT6; //track the time course of XT1 stabilization
    // Loop until XT1, XT2 & DCO stabilizes
    do
        {
            UCSCTL7 &= ~(XT2OFFG | XT1LFOFFG | DCOFFG);
            // Clear XT2,XT1,DCO fault flags
            SFRIFG1 &= ~OFIFG;             // Clear fault flags
        } while (SFRIFG1 & OFIFG);         // Test oscillator fault flag
    UCSCTL6 &= ~(XT1DRIVE_3);              // XT1 stable, reduce drive strength

    P4OUT ^= BIT6;          //track time course of XT1 stabilization
   
    //UCSCTL4 |= SELM__DCOCLK;      // MCLK: DCOCLK, SMCLK & ACLK default to DCOCLKDIV and XT1CLK
    __bis_SR_register(SCG0);               // Disable the FLL control loop
    UCSCTL0 = 0x0000;                      // Set lowest possible DCOx, MODx
    UCSCTL1 = DCORSEL_5;                   // Select DCO range 16MHz operation
    UCSCTL2 = FLLD_2 | 127;                // fDCOCLK = 4 * (127 + 1) * 32768, DCO 16MHz, DCODIV, 4MHz
    __bic_SR_register(SCG0);               // Enable the FLL control loop
    UCSCTL4 |= SELM__DCOCLK;      // MCLK: DCOCLK, SMCLK & ACLK default to DCOCLKDIV and XT1CLK

    int i = 0;
    while (1)
       {
           P4OUT ^= BIT6;                  // Toggle P4.6
           for ( i = 0; i < 1000; i++)
           __delay_cycles(16000);          // Delay 1 ms * 1000 = 1s
       }
 return 0;
}

The toggle rate of LED is supposed to be 1s on -- 1s off. The actual rate was measured at 4s on -- 4s off. I also changed

UCSCTL2 = FLLD_1 | 243;                // fDCOCLK = 2* (243 + 1) * 32768, DCO 16MHz, DCODIV = 8MHz

In this case, LED toggle rate was measured at 2s on and 2s off.

In both cases, the most reasonable explanation is that MCLK is sourced from DCOCLKDIV. I think I am missing something here but cannot figure what it exact it is.

So please advise.

Thanks in advance.

ZL