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SD16_A input voltage range

Paul Lander
Prodigy 230 points
Other Parts Discussed in Thread: MSP430F47166, MSP430F2013

The MSP430F47166 has the following datasheet specifications:

  1. AVCC is 2.5V - 3.6V, referred to AVSS = DVSS = 0V
  2. With VREF = 1.2V and the PGA set to gain=1, the full-scale differential input voltage is -0.6V to +0.6V, relative to VREF, i.e. +0.6V to 1.8V referred to AVSS
  3. Absolute input voltage range = AVSS-1V to AVCC, e.g. -1.0V to +3.6V
  4. Absolute maximum ratings, voltage applied to any pin is -0.3V to VCC+0.3V, referred to "VSS", e.g. -0.3V to +3.9V

Two questions:

  1. Does spec #3 conflict with #4 above, or is AVSS > DVSS allowed?
  2. A silicon diode connected from A0.0+ to VREF would limit the negative voltage swing to VREF - VDIODE, is this necessary or is A0.0+ ESD protected if current limited?
  • 0
    TI__Expert 7605 points

    Hello Paul,

    Very good observations. I think you found a place where we are not 100% crystal clear. Regarding your questions:

    1- Definitely connect AVss = DVss = GND; no conflict. However, the analog inputs for the sigma-delta on this particular device are designed in such a way as to allow a -0.6V (relative to A/DVSS) value to be directly input to the ADC. On these pins there is the exception to the absolute spec requirement of -0.3V min applied voltage. This capability saves external offset circuitry that otherwise might be needed to offset the input voltage above the 0V AVss level. Keep in mind this is only on some MSP430 SD16/AD16_A devices. For example, the MSP430F2013 does not have this capability and the spec for absolute minimum voltage on the SD16 inputs is AVss - 0.1V.

    2- All pins are ESD protected. But the absolute input range is still AVss -1V to AVcc. The reference voltage itself determines the min/max differential voltage that can be applied (along with the gain).

    I hope this helps answer your questions, Zack

  • 0 in reply to Zack A
    Prodigy 230 points

    Hi Zack,

    Crystal clear now, thanks.  An in-range negative input voltage (w.r.t. AVSS) is undersold by TI and is a big plus for the F4xx parts, so to speak!  We contemplate 2 approaches:

    1. Use a split supply (+/-2.5V), amplify a signal referenced to AVSS=A0-, and put a silicon diode in the feedback loop of the last amplifier stage to limit the output voltage between -0.7V and +2.5V.  The advantage of this approach is the high PSRR and low distortion (noise) added to small signals from sensitive transducers.  The disadvantage is having to provide current from -2.5V.
    2. Use a single supply (0 to 3.6V) and use VREF as the input signal reference for the op-amp circuitry and at A0-.  Advantage, simple LDO power supply.  Disadvantage, any noise on VREF is partially fed into the amplified signal, even when that signal is referenced to VREF at A0-.

    The graphs below show the 100-microsecond rise time of VREF (as the datasheet predicts) and an amplified, dc-adjusted impulse signal:  AVSS is at cursor 1, quiescent signal level=VREF.  Two questions that explore noise performance and help decide between #1 & #2 above are:

    1. What is the 3-dB noise bandwidth and RMS value of the VREF pin output?  (At a guess, about 3,000Hz and a few microvolts?)
    2. What is the Thevenin equivalent noise source resistance, looking into the VREF pin?  (At a guess, a few ohms at most, looking into an op-amp output?)

    Paul

     


     

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