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MSP430F479 DAC stable question.

Other Parts Discussed in Thread: MSP430F479

Dear Sir

Good afternoon,
I used the MSP430F479 DAC, found a phenomenon,

it must be initialized twice, so that the output value is stable All products are available at + - 2 LSB.

If the initialization only once, there will be 15% of the products appear tolerance of 3 ~ 5 LSB,
I tried to adjust the timing of DAC12 CALON, but to no avail, I ask, how could this happen?

The following is my test initialization code:

//==========================================================================

 // Repeat the following code twice will be stable DAC output..
//===========================================================================

void SD16A_DAC12_ON()

{

    SET_AdPower_ON;

    SD16CTL = SD16REFON+SD16VMIDON+SD16SSEL0+SD16DIV_3;            // 1.2V ref, MCLK/8, Vref buffer ON

    SD16CCTL0 = SD16SNGL+SD16BUF_3;                                  // 0~32787, high speed current

    __delay_cycles(614754);// delay cycles times

 

    DAC12_0CTL = DAC12IR + DAC12SREF_3 + DAC12AMP_5 + DAC12OPS + DAC12ENC + DAC12CALON;      // DAC12AMPx = 5 , Input Buffer Medium speed/current ; Output Buffer = Medium speed/current

    DAC12_0DAT = g_uiDigiDAC0;

    __delay_cycles(614754);// delay cycles times

}

 //=================================================================================

thanks a lot.

Wilson_WT

  • Dear Wilson_WT,
    Thank you for sharing this. The DAC12_0CTL register has a number of fields that can only be modified when DAC12EN is 0, so it does not make sense that repeating the instruction (after setting DAC12EN the first time) would have any impact.

    After the first initialization can you read out the contents of the DMA registers?  Also, can you confirm that you only see the issue on ~15% of your products? And finally, can you share the silicon revision?

    Thanks and Regards,
    Chris

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