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MSP430 reset specification

Other Parts Discussed in Thread: MSP430F5171
Hi,
 
This is about the MSP430's reset, 
On the MSP430F5171 datasheet, 
the reset pulse duration time is mentioned as tRESET=2us(min), 
but falling edge timing is not mentioned in the datasheet. 
Please let me know is there is any details about the falling edge specification?
 
The background of this question is.
 
Our customer's MSP430F5171 reset line is connected to a FPGA, and
reset signal is controlled by that FPGA.
Currently, MSP430F5171 freezes/stalls if the reset falling edge is 1us.
But it works normal if they increase the reset signal falling time to 1ms
through an open collector transistor base CR time constant.
 
This stall condition cannot be recovered without a POR.
 
We also concerned about undershoot issue of this signal.
Please let me know if an under shoot signal could stall MSP430?
 
Thanks and BRs,
 
  • Hi tmatsu,

    Can your customer please provide some oscilloscope shots of the RST line (for both 1 us and 1 ms)? How long is the reset line held low before being brought up again? How much capacitance is on the RST line, and are there any other passive components on said line? Typically there is a 47 kOhm pull-up resistor and 2.2 nF capacitor to GND.

    Regards,
    Ryan
  • Aside from the pull-up resistor and pull-down capacitor that Ryan mentioned, if you want to control it with a FPGA output pin that FPGA pin should go to high-impedance normally and be active low for only a few micro-seconds.

    What is the value of the pull-down capacitor used? It may be too big (as compared with 2.2 nF).
  • Hi, Ryan-san, old_cow_yellow-san,

    Thank you for the quick reply.
    Our customer's circuit is as per the TI reference.
    47k pull up resistor and 2.2nf capacitor.

    Will ask the customer to check the oscillator waveform. Meanwhile please let me know if there is
    anything else to be checked.

    Best Regards,
  • To Reset the MSP with a FPGA output pin connected to MSP RST pin, the oscillator waveform is not relevant.

    The FPGA pin must be normally in "tri-state" (as in open-collector). When Reset is desired, that pin must go to "active -low" for a few micro-second and then back to "tri-state".

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