Hi,
This is about the MSP430's reset,
On the MSP430F5171 datasheet, the reset pulse duration time is mentioned as tRESET=2us(min),
but falling edge timing is not mentioned in the datasheet.
Please let me know is there is any details about the falling edge specification?
The background of this question is.
Our customer's MSP430F5171 reset line is connected to a FPGA, and
reset signal is controlled by that FPGA.
Currently, MSP430F5171 freezes/stalls if the reset falling edge is 1us.
But it works normal if they increase the reset signal falling time to 1ms
through an open collector transistor base CR time constant.
This stall condition cannot be recovered without a POR.
We also concerned about undershoot issue of this signal.
Please let me know if an under shoot signal could stall MSP430?
Thanks and BRs,