Hi community member,
Please let me confirm the following a question for SPI interface of EEPROM Emulation with MSP FRAM.
[Question]
Regarding to the TI Designs (EEPROM Emulation and Sensing With MSP FRAM Microcontrollers Design Guide),
there must be a minimum of 20us delay between EEPROM address to first data.
> Unlike traditional EEPROM, an key integral difference is that there must be a minimum of 20-μs delay.
after writing the 3-byte address before starting the next clock edge for data to be written.
why must be a minimum of 20us delay?
Is there a way to make Delay shorter than 20us?
Best regards.
Cruijff
