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MSP430F6733: Is it necessary to clear the interrupt flag(s) before entering LPM4 ?

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Part Number: MSP430F6733


Hello,
Is it necessary to clear the interrupt flag(s) before entering LPM4 ?
(Necessary / preferable / not necessary ?)

Our question above is an important point of customer's logic, so please reply whatever your advice to the background problem would be. Please.



(background)
Me and my customer are debugging a released code. We are required to explain an issue mechanism.
Their symptom is "Unable to jump from LPM4 to the P2.4 GPIO ISR."
    __bis_SR_register(LPM4_bits + GIE);

We are studying the UG slau208p.pdf, p66-68.


For LPMx.5, the "Note" recommends to clear the interrupt flags as follows:

p.68 - - -
NOTE: It is not possible to wake up from LPMx.5 if its respective interrupt flag is already asserted.
TI recommends clearing the respective flag before entering LPMx.5. TI also recommends
setting GIE = 1 before entry into LPMx.5. Any pending flags in this case could then be
serviced before LPMx.5 entry.
Although TI recommends setting GIE = 1 before entering LPMx.5, it is not required. Device
wakeup from LPMx.5 with an enabled wake-up function will still cause the device to wake up
from LPMx.5 even with GIE = 0. If GIE = 0 before LPMx.5, additional care may be required.
Should the respective interrupt event should occur during LPMx.5 entry, the device may not
recognize this or any future interrupt wake-up event on this function.

This note is just for LPMx.5 but no comment found for LPM4. So we are asked whether the TI recommendation is true or not for LPM4.




(Progress for the troubleshooting itself)
I could not duplicate the phenomenon "Unable to jump from LPM4 to the P2.4 GPIO ISR."
So I will visit my customer to see customer code tomorrow.

My progress would be reported again. anyway, my question on the top of this msg is important today. Your response is highly appreciated.




p.s. We are aware of that the interrupt detection is not level but edge based. My customer repeated toggling P2.4 to try to see a jump to ISR.

  • LPMx.5 is quite different becuase the power is switched off, and the interrupt system is reinitialized after the wake-up event.

    In LPM4, all the configuration remains, only the clocks are switched off. So to be able to wake up, GIE must be set (which you're alread doing). If your interrupt flag is set, this will cause the CPU to wake up immediately to handle the interrupt. So it is not necessary to clear any interrupt flag(s) before going into LPM4.

    Your problem might be caused by erratum PMM15.
  • In reply to Clemens Ladisch:

    Clemens,
    Thank you for your reply. We started to study PMM15.
    Once I would close this. Please help if resumes.

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