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MSP430FR5994: DMA/FRAM Wake up charge from LPM3

Part Number: MSP430FR5994
Other Parts Discussed in Thread: ENERGYTRACE

Hi, 

im trying to make sense of the wake up figures in the datasheet. I measured around 23nC for wake up from LPM3 which is close to the figure below (but a bit confused about the extra FRAM wake up charge). 

I have written other code to transfer bytes using the DMA, from one RAM location to another, from LPM3 using ALCK->TIMERB to trigger it. with no interrupts except pressing a button. Im using 8MHz for M/SMCLK.

i measured around 18nC to wake the DMA. but i thought it would be lower. Although, comparing LPM0 and LPM3 in table 1-2 (register bits) and table 5-10(wake up charges), the difference between them waking up is reconfiguring the DCO/MCLK. The commonality is waking the CPU.  Therefore it seems like the DMA wake-up charge from LPM3 should be similar to QWAKE(LPM3) - QWAKE(LPM0), as the DMA has to wake/configure the DCO, request clock for the bus, but doesn’t wake the CPU.

Therefore the expected wake up charge is expected to be 25-3.8=21.2nC:

                        Expected QWAKE(DMA) ~ 21nC

have i understood that correctly?

Also, the wake up time based on table below for LPM3 (based on 3 cycles, as im ignoring the 2 cycles per transfer) would be 5.375us.  the wake up time for LPM3->active at 8MHz is 6.85us. 

5.375/6.85 * 23nC = 18nC which seems a strong clue as well. 

I configured the PJ.x bits to output the SR bits. They dont change but i guess thats expected, the DMA onverules the bits to wake the DCO/MCLK clock as necessary? The users guide says SCG1/0 are device dependant, and SCG1 "for example" is DCO bias enable, and SCG0 "for example" is FLL enable. Would like to know for sure, but can't find anything in the datasheet. 

DATASHEET FIGURES:

FRAM wake up = 16.5nC.

LPM0 wake up = 3.8nC

LPM3 wake up = 25nC

Measured figures (Measured the average current at different frequencies (A) then divided by frequency (1/s) to get charge per event (As)):

LPM3 wake up ~= 23nC 

DMA wake up  ~= 18nC  (y intercept from below)

thanks. 

  • Mickovich,

    I have received your question. I will get back to you shortly.
  • Dear Mickovich,

    There are many questions so please reply if I missed something.
    1. The wake up time from LPM3 is "typically" 6.85us. But it could be anywhere up to 9.912 us. In fact it is not acceptable to assume that 6.85 is the absolute value. So please take that into your calculations.
    2. The DMA will take priority to turn on and configure the DCO/MCLK. The DMA will not require CPU.
    3. The extra FRAM wake up charge is not relevant to your testing because you did not mention having disabled the FRAM through FRAM controller.
    4. The difference from LPM3 to LPM0 can be dependent on whether or not you use SMCLK.
    5. As far SCG0 and SCG1, even though the datasheet does not mention anything about it, I believe they still are FLL and DCO bias enables.
  • Hi Nima,

    Many thanks for the response.

    Sorry for the long winded questions, the main question i have is what is the expected wake-up charge of the DMA?

    I was wondering if i could get a estimate of this from a difference between some values for charge in table 5-10.

    3. FRAM controller. i wasnt sure if the 'Qwake-up FRAM' was the charge needed when it is accessed. its not clear the definition of 'FRAM active' in table 5-10.  i.e. in LPM0-4 table 5-10 says "with fram active", but the FPWR description below says that it automatically goes to INACTIVE.  

    I have tried with and without FRPWR set, and there is no change in the measured current.

    FRPWR Bit

    While the device is in AM (Active mode), the FRAM memory power is controlled by the FRPWR bit and FRAM access. When the FRPWR is set, the FRAM memory is in ACTIVE mode. When the FRPWR is cleared by CPU, the FRAM memory goes into INACTIVE mode so that the FRAM memory does not consumes power.

    The INACTIVE mode can be used if no FRAM access is required for a significant amount of time. Once the FRAM memory is in the INACTIVE mode, wake-up is automatic. An access to FRAM (read or write) will wake up the FRAM memory before performing the access. In this case, the FRPWR bit is set automatically by the FRAM controller.

    When the device enters LPM0/1/2/3/4 modes, the FRAM memory also enters INACTIVE mode regardless of the FRPWR bit status. When the device wakes up from LPM0/1/2/3/4, the FRAM memory will be immediately powered up (ACTIVE mode) if the FRPWR is set, but if the FRPWR bit is cleared, the FRAM memory will remain in INACTIVE mode until the FRAM memory is actually accessed (read or write). The latter case can be used to save the device power consumption in case the device wakes up only for a short amount of time, and the task during the wake-up can be executed from RAM, so no need of FRAM access. 

    4. I haven't set the SMCLK to be used by any peripherals, and i opened EnergyTrace which didnt show it waking up.  

    Regards,

    Michael.

  • Dear Mickovich,

    The FRAM will enter inactive mode when you enter LPM mode and when you wake up, if the FRPWR is cleared, UNLESS you use the FRAM it will not wake up.

    We do not have measurements for the DMA wake up charge. It should be measured on your side and based on what I see in your calculation, it matches the wake up charges we provide in the datasheet.

  • Hi Nima,
    Just to confirm, do you mean my assumption that the DMA wake should be similar to QWAKE(LPM3) - QWAKE(LPM0) is correct? or do you mean other charges you provide in the datasheet.

    im still not clear on the FRAM, if it wont wake unless used - should the wake up charges Qlpm0-3 in table 5-10 not include anything to do with FRAM? i.e. they say "with FRAM active" but this actually means "without FRAM wake up"?

    I just want to be 100% sure, in case there is something i havent set up right in code that could reduce the DMA wake up charge further.
    Another way to interpret the table 5-10 could be that DMA wake up should be QWAKE(LPM3) - QWAKE(LPM0) - QFRAM ~= 4.7nC, if those figures include for Qlpm0-3 include waking up FRAM?

    Regards,
    Michael.
  • Michael,

    Based on my understanding of the low power modes and FRAM, the wake up charge for DMA should be similar to QWake(LPM3) - QWake(LPM0). Use the QWake(LPMx) with FRAM Active to have the only variable be the difference between LPM0 and LPM3 (Which will include the DMA). I agree with your initial calculations as long as you take into account the fact that these are "typical" values and they could possibly be higher or lower.
  • hi Nima,

    thanks for the help.  i appreciate these are typical values, i just want to get familiar with how it works.  

    i have since got the DMA charge much lower. Previously, I was clearing the FRPWR bit in initialisation. but the CPU sets it again with any FRAM access (i.e. waking up and running code). i had thought this was just an 'override' and it would go back to being clear again when going back to sleep, but it doesn't.  so in my test code as soon as i press a button to change something, it is set. Then it seems that any DMA wake up activates the FRAM even though it isn't using it.  

    i've added code to clear the FRPWR bit before every sleep.  I'm now getting around 3nC for DMA wake up.

    [Although not 100% clear on why the next line (go to sleep instruction) does not constitute a FRAM access and clear the FRPWR bit again. I think it is to do with pipelining / cache?]

    Cheers,

    Michael. 

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