This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Compiler/MSP430F4152: MSP430 Working Frequency

Part Number: MSP430F4152

Tool/software: TI C/C++ Compiler

Hello everyone,

MSP430 offer different clock source on different module is exactly right.

For instance, one can choose MCLK, ACLK or SMCLK as the clock base for Timer A.

And my question is about what frequency is the base clock for MSP430 working.

I usually use 32.768 KHz or no crystal for MSP430.

But no matter I use crystal or not, MSP430 can work all the time.

These are my questions,

  1. How can I know the frequency for the MSP430 working?
  2. How can I choose the frequency for the MSP430 working? I need to make MSP430 work with a higher speed.
  3. Can I replace the crystal with a high-frequency crystal, 11.0592 MHz or more higher?
  4. If I can replace the crystal with a high-frequency crystal, will other frequency (MCLK, ACLK, SMCLK, etc.) or operation be changed?

Sincerely,

Norton

  • Hi Norton,

    I recommend reading through Section 5 of the MSP430x4xx Family User's Guide. You can find the majority of the information you are looking for there. This section fully describes the clocking system within the MSP430F4152 and how to change system frequency. At startup ACLK, SMCLK, and MCLK stabilize to ~1MHz.

    Looking at the crystal oscillator, LFXT1, high frequency modes section of MSP430F41x2 Mixed Signal Microcontroller you can also see that the maximum frequency for an external crystal is 6 MHz.

    Finally, you can find examples of how to setup the clocking system for this MSP430 here.

    Best regards,

    Caleb Overbay

  • Hi Caleb Overbay,

    Thanks a lot.
    Still now, I have known that there is a sample code of MCLK control in sample code.
    I will check on it, Thanks a lot.
    If there is other question or trouble, I will let you know.

    Sincerely,
    Norton
  • Hi Norton,

    To summarize your message that was sent to me:

    Yu-Chuan Chen said:

    I have replace the crystal with 4MHz.

    After I finished changing the register, I use P1SEL to output the MCLK.

    I do not use and divider or lock loop, but my output frequency has only 3MHz.

    Are there anything wrong about my setting?

    These are mt code below,

    FLL_CTL0 |= XTS_FLL;
    FLL_CTL1 |= SELM_A;
    FLL_CTL2 |= LF1XT1S_2;

    BTW,

    when I use lock loop to make the frequency more higher.

    It has only 7MHz.

    This is my setting code,

    SCFI0 |= FN_8 + FLLD_8;

    Sincerely,

    Norton

    There are quite a few things wrong with this approach:

    1. When using an external crystal, you should always check that the crystal is stable before executing any code.
      1. Example MSP430x41x2_clks.c shows how this is accomplished
    2. There is no need to set the FLL_CTL2 register
      1. According to the user's guide, when XTS_FLL = 1, FLL_CTL2 is reserved
    3. Do you have the appropriate external load capacitance for your crystal?
      1. This could be keeping the crystal from oscillating at the correct frequency
      2. When using the LFXT1 in high frequency mode, you should not use internal capacitance
    4. Using FLL_CTL1 |= SELM_A; you are setting MCLK = LFXT1 = 4MHz
      1. When using the FLL to set the DCO, you won't see a change on MCLK if you keep this setting
    5. When using SCFI0 |= FN_8 + FLLD_8; it looks like you are trying to set the DCO to > 32MHz but the Max system frequency on the MSP430F4152 is 8MHz. 
      1. Additionally, When DCOPLUS = 0 then fDCOCLK = (N+1) * fCRYSTAL and when DCOPLUS = 1 then fDCOCLK = D*(N+1) * fCRYSTAL
      2. Because you never set DCOPLUS you are using the first equation and the value you set for FLLD_8 is never applied to the DCO frequency
    6. Finally, when using the FLL you have to ensure the value of N in the SCFQCTL register is set appropriately.

    Best regards, 

    Caleb Overbay

  • Hi Caleb Overbay,

    Thanks for your kind attention for reply and your help.
    According to your reply, I want to make some check with my understanding.

    1. Do you have the appropriate external load capacitance for your crystal?
      >> There is no appropriate external load capacitance for my crystal.
      >> Maybe this would be one of the problem of my trouble.
    2. Using FLL_CTL1|=SELM_A; you are setting MCLK=LFXT1=4MHz
      When using SCFI0|=FN_8+FDDL_8; it looks like you are trying to set the DCO to > 32MHz but the MAX system frequency on the MSP430F4152 is 8MHz.
      >> If I use FLL_CTL1|=SELM_A; The MCLK will be the external crystal and it can not be higher, right?
      >> According to the data sheet, MAX support of crystal is 6MHz, and MAX MCLK support is 8MHz.
              If I need the highest frequency of this chip, the best choice is set MCLK=DCO?
    3. Finally, when using the FLL you have to ensure the value of N in the SCFQCTL register is set appropriately.
      >> When I need to use FLL, the only source of CLK is DCO right?
      >> I check with P5-7 of data sheet which is MSP430Fx4xx Family, I can only know that there are Dividers on ACLK path and DCO path.
      >> The Divider of ACLK is make the ACLK to /2, /4, or /8. And the Divider of SMCLK is make the SMCLK to *2, *4, or *8

    All the above is combined with your reply and my understanding.

    And I will try with this method, Are there anything wrong with these description?


    Sincerely,
    Norton

  • Hi Norton, 

    Yu-Chuan Chen said:
    There is no appropriate external load capacitance for my crystal. Maybe this would be one of the problem of my trouble.

    Typically on the crystal's datasheet it will specify the effective load capacitance. You'll need to populate this on the board according to section 2.1 of MSP430 32-kHz Crystal Oscillators.

    Yu-Chuan Chen said:
    If I use FLL_CTL1|=SELM_A; The MCLK will be the external crystal and it can not be higher, right?  According to the data sheet, MAX support of crystal is 6MHz, and MAX MCLK support is 8MHz. If I need the highest frequency of this chip, the best choice is set MCLK=DCO?

    Correct, if selecting MCLK = ACLK= LFXT1 then the highest frequency for MCLK could be 6MHz. The best option for reaching 8MHx is to use the FLL with a 32768Hz crystal oscillator as a reference to stabilize the DCO. 

    Yu-Chuan Chen said:
    When I need to use FLL, the only source of CLK is DCO right? I check with P5-7 of data sheet which is MSP430Fx4xx Family, I can only know that there are Dividers on ACLK path and DCO path. The Divider of ACLK is make the ACLK to /2, /4, or /8. And the Divider of SMCLK is make the SMCLK to *2, *4, or *8

    The FLL is used to stabilize the DCO and you need to provide it a reference clock source. This is typically a 32kHz crystal but a 6MHz crystal can be used as well. You're correct that the ACLK has a divider in its path. This is because it doesn't use the FLL and can't reach all the frequencies that the MCLK/SMCLK can. You don't see a divider in the SMCLK or MCLK path because you can use the FLL to reach a desired frequency. 

    Best regards, 
    Caleb Overbay

  • Hi Caleb Overbay,

    I've got the datasheet of 32KHz Crystal.
    I will check on it and do some change on my hardware.
    Thank you so much.

    Sincerely,
    Norton

**Attention** This is a public forum