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MSP430G2744: UCA0/UCB0 Spi Master/Slave Interface

Dietrich Wall74
Prodigy 60 points
Part Number: MSP430G2744

Hello,

We need to operate a MSP430G2744 with 2 USCIs in Spi Mode, One Interface will act as a Slave in a multislave environment along with other MSP430 Slave devices. The other Interface will act straightforward as Master with one Slave device. 

I have some questions regarding the Slave Interface. (UsciA0)

As far as I understood the User Guide and Datasheet, the device will release the MISO Signal  and go to high Impendance mode, whenever the STE Signal becomes inactive. I haven´t found anything what describes what happens with MISO if SPI is in 3 Wire configuration. (STE Signal is not asserted to the Slave USCI Module)

Does it mean USCI never releases the MISO Pin when STE is not asserted to the Module, and MOSI will stay in the State of the last transmitted Bit?

The STE Signal is routed to Pins 3.0/3.3. Both Pins share the STE Function with CLK Signal of other Module.  Do we need some concepts to prevent shortened circuits on MISO Line?

Is the function of the STE signal the same as an usual Chip Select Signal?

Greetings 

Dietrich

  • 0
    TI__Genius 15370 points

    Hi Dietrich, 

    Dietrich Wall74 said:
    Does it mean USCI never releases the MISO Pin when STE is not asserted to the Module, and MOSI will stay in the State of the last transmitted Bit?

    I believe the MISO line will retain the state of the last transmitted bit but I need to confirm this.

    Dietrich Wall74 said:
    The STE Signal is routed to Pins 3.0/3.3. Both Pins share the STE Function with CLK Signal of other Module.  Do we need some concepts to prevent shortened circuits on MISO Line?

    I'm not sure what you mean by shortened circuits on the MISO line here. However, if you intend to use both USCI_B and USCI_A for SPI communication at the same time, you can't use the STE functionality. You'll instead need to use a GPIO for this signal.

    Dietrich Wall74 said:
    Is the function of the STE signal the same as an usual Chip Select Signal?

    From a slave perspective, the STE signal is identical to a CS signal. However, from a master point of view there is a key difference. Typically a master will hold the CS signal in the desired state throughout all bytes of a transaction. On an MSP430 SPI master, the STE signal will revert to the "inactive" state between each byte sent but will automatically be set to the "active" state when a byte is transmitted. 

    Best regards, 
    Caleb Overbay

  • 0 in reply to Caleb Overbay
    Prodigy 60 points
    Hi Caleb
    thank you, this clarifies some, but not everything.
    I would describe shortened circuit as following: One Msp430 SPI slave has transmitted a logic 1 as last bit, and keeps MISO high , the other has transmitted a logic 0 as last bit and tries to pull the MISO line down to ground.
    Please confirm it isn´t possible to resolve this issue when SPI is in 3 wire slave mode. Either the MSP Software will need to toggle MISO line between input and USCI for transactions, or we will need some additional external parts, which automatically resolve this.
    Dietrich
  • 0 in reply to Dietrich Wall74
    TI__Genius 15370 points

    Hi Dietrich, 

    I wanted to let you know I'm working with our internal systems team to answer this question. They have a better understanding of how the SOMI line behaves in 3-pin mode. I'll update you as soon as we come to a solution. Thanks for your patience.

    Best regards, 
    Caleb Overbay

  • 0 in reply to Dietrich Wall74
    TI__Genius 15370 points
    Hi Dietrich,

    I apologize for the long delay. I have been able to verify that the SOMI line will retain the last logic state transmitted when the clock becomes inactive in 3-pin mode. Additionally, when the clock becomes active again data will always be transmitted from the MSP430 when in 3-pin SPI mode regardless of whether data has been placed in the TX buffer. My suggestion is that you disable the SPI functionality for the SOMI pin when the CS signal is inactive. This can be done by clearing the respective PxSEL bits for the SOMI pin. This will not allow the SPI module to control the pin. Then when the CS is active, re-enabling the pin via the PxSEL bits.

    Best regards,
    Caleb Overbay
  • 0 in reply to Caleb Overbay
    Prodigy 60 points
    Hi Caleb,
    Thank you this makes it clear
    Best regards,
    Dietrich

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