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MSP430FR2433: Some ports can not keep output when LPMx.5

Massa1
Expert 1050 points
Part Number: MSP430FR2433
Other Parts Discussed in Thread: MSP-FET, MSP-TS430RGE24A

Hi, all;

I am evaluating the x.5 low power mode of MSP430FR2433.

To evaluate keeping output, I set all GPIO port to OUTPUT-HIGH as:

P1OUT = 0xFF; P2OUT = 0xFF; P3OUT = 0xFF;

Then I can confirm all bits are High.

However after FR2433 execute "__bis_SR_register(LPM3_bits | GIE);"  , P1.4, P1.5, P1.6 and P1.7 become Hi-Z.

This means port P1.4 to P1.7 can not keep output status in LPM3.5 and LPM4.5.

It seems as P1DIR was reset.

Another pins, P1.0-P1.3, P2.0-P2.7, P3.0-P3.2 can keep OUTPUT-HIGH and work okay.

When setting OUTPUT-Low, the results are same and P1.4 to P1.7 become Hi-Z.

I can not find this issue in errata sheet.

Can I find any workaround, or we can not use P1.4 to P1.7 when LPMx.5?

My environments are CCSv7.3, MSP-FET, MSP-TS430RGE24A, MSP430FR2433IRGE Rev.A.

  • 0
    TI__Intellectual 1995 points
    Hi Massa1,

    May I know if you are using debug mode when running your code? Have you tried free run? please note that LPMx.5 not support debugging.

    regards
    KC
  • 0 in reply to KC Xu
    Expert 1050 points

    Hi KC,

    thanks for your response.

    I found the issue in debugging mode with SBW.  Because I wanted to check every port behaviors step by step.

    Now I tried to run without SBW and the ports seemed to work good.

    I wonder the bit behaviors will change in debug mode!

    I will continue to check LPM3.5 ports with free run mode.

    Thank you and B.R.

    Massa

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