This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TDO/TDI pin of MSP430F47176

Other Parts Discussed in Thread: MSP430F47176

I have a question about pins of MSP430F47176.

 

According to pdf file (msp430f47176.pdf) page 10, there are two pins which used as "TDI".

That is, PIN96 (TDO/TDI) and PIN97 (TDI/TCLK).

 

The pdf shows that

TDO/TDI (pin 96) -- Test data output port. TDO/TDI data output or programming data input terminal.

TDI/TCLK (pin 97) -- Test data input or test clock input. The device protection fuse is connected to TDI/TCLK.

 

Is the TDI of pin 96 used only for program downloading from PC to MSP? Or are there any other occasion where

data is transferred from MSP to PC, such as during debug mode?

 

 

  • JTAG is a relatively complex thing, desinged to do much with few lines.

    Take a look at the schematic in on page 78 of the device datasheet (revision b) any you'll see that the pins have different meaning depending on the current state of the JTAG internal state machine. In some configuraiton, the JTAG interface can use TDO as TDI id TDO is not required, or use it as TDO->TDI loopback. Maybe this is required for device-chaining or whatever.

    In any case, it is not used for program downloading with the boot strap loader (it uses two normal portpins to emulate a serial connection).

    These pins, however, can be used to manipulate the CPU and al in its address space, and yes, it is required for debugging as well as it can be (and is) used for program downloading. In downlaod mode, the programming software places byte for byte a small program along with a fraction of the application into the device ram (by forcing the CPU core to do the necessary operations), sets a breakpoint at its end and changes the CPU program counter, so the CPU will execute the injected code. This code then code this small portion of the applicaiton into flash. Then the process is repeated for the next code snippet until all is done.

    If you don't want to develop a JTAG programmer, ignore these pins.

    On other MSPs (usually iwth a low pin count), these pins are connected to normal port pins and an external TEST pin switches between port and JTAG functionality. The JTAG part, however, is an independent piece of hardware inside the MSP and cannot be accessed ot controlled by the CPU. On the contrary it is designed to control the CPU instead..

  • Thank you very much for your reply, Jens-Michael.

     

    Jens-Michael Gross said:

    the JTAG interface can use TDO as TDI id TDO is not required, or use it as TDO->TDI loopback.

     

    Does your above description mean that there are 2 functions in TDO/TDI pin (i.e.  as TDI, and as TDO->TDI loopback)?

    I checked the pdf file of revision b, page 78. Is it possible to receive inward data through TDO line of TDO/TDI part?

    There is a buffer circuit just outside the TDO/TDI pin of JTAG. Doen't this buffer circuit prevent the inward data?

     

     

     

     

  • Inside the top right dashed-line box and at the extreme right, the  |=> is the TDO/TDI bi-directional pin. The signal TDO at the left side of that box is output only. Yes, there is a buffer between them to deliver TDO output signal to TDO/TDI pin.

    But the next dashed-line box below, there is the input signal TDI. There is a electric-switch (controlled by JTAG logic) that can connect to the TDO/TDI pin through an OR gate. Thus DTO/TDI pin can also be used as an input pin to the internal TDI input signal.

  •  

    Thank you very much, old_cow_yellow.

     

    I could clearly understand the figure.

     

    Best regards

     

**Attention** This is a public forum