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SIMPLELINK-MSP432-SDK: Simple Link DriverLib SPI Interrupt Flags

Part Number: SIMPLELINK-MSP432-SDK

I have code that was getting optimized out because I believe there is a macro definition issue in the MSP432 SimpleLink DriverLib.

I'm using : simplelink_msp432p4_sdk_2_10_00_14

I get the interrupt flags from SPI_getEnabledInterruptStatus

//*****************************************************************************
//
//! Gets the current SPI interrupt status masked with the enabled interrupts.
//! This function is useful to call in ISRs to get a list of pending
//! interrupts that are actually enabled and could have caused
//! the ISR.
//!
//! \param moduleInstance is the instance of the eUSCI A/B module. Valid
//! parameters vary from part to part, but can include:
//!         - \b EUSCI_A0_BASE
//!         - \b EUSCI_A1_BASE
//!         - \b EUSCI_A2_BASE
//!         - \b EUSCI_A3_BASE
//!         - \b EUSCI_B0_BASE
//!         - \b EUSCI_B1_BASE
//!         - \b EUSCI_B2_BASE
//!         - \b EUSCI_B3_BASE
//!
//! Modified registers are \b UCAxIFG.
//!
//! \return The current interrupt status as the mask of the set flags
//! Mask parameter can be either any of the following selection:
//! - \b EUSCI_SPI_RECEIVE_INTERRUPT -Receive interrupt
//! - \b EUSCI_SPI_TRANSMIT_INTERRUPT - Transmit interrupt
//
//*****************************************************************************
extern uint_fast8_t SPI_getEnabledInterruptStatus(uint32_t moduleInstance);

Note in the comment refers to (EUSCI_SPI_RECEIVE_INTERRUPT and EUSCI_SPI_TRANSMIT_INTERRUPT). 

These mask macros are also used by:

  • SPI_getInterruptStatus
  • SPI_disableInterrupt
  • SPI_enableInterrupt

When i look at how the macros are defined you get the following in (ti/simplelink_msp432p4_sdk_2_10_00_14/source/ti/devices/msp432p4xx/driverlib/spi.h)

#define EUSCI_SPI_TRANSMIT_INTERRUPT    EUSCI_B_IE_TXIE_OFS
#define EUSCI_SPI_RECEIVE_INTERRUPT     EUSCI_B_IE_RXIE_OFS

Now the concern is  EUSCI_B_IE_TXIE_OFS and EUSCI_B_IE_RXIE_OFS refer to bitmap offsets rather than the bitmap value.  This can be seen in: (ti/simplelink_msp432p4_sdk_2_10_00_14/source/ti/devices/msp432p4xx/inc)

/* EUSCI_B_IE[RXIE] Bits */
#define EUSCI_B_IE_RXIE_OFS                      ( 0)                            /*!< UCRXIE Bit Offset */
#define EUSCI_B_IE_RXIE                          ((uint16_t)0x0001)              /*!< Receive interrupt enable */
/* EUSCI_B_IE[TXIE] Bits */
#define EUSCI_B_IE_TXIE_OFS                      ( 1)                            /*!< UCTXIE Bit Offset */
#define EUSCI_B_IE_TXIE                          ((uint16_t)0x0002)              /*!< Transmit interrupt enable */

Note that EUSCI_B_IE_RXIE_OFS which defines EUSCI_SPI_RECEIVE_INTERRUPT is 0, so any mask checks against it, will always fail.  So the code below was always getting optimized out.  

   if( flags & EUSCI_SPI_RECEIVE_INTERRUPT )
   {
      /* USCI_B0 TX buffer ready? */
      while (!(SPI_getInterruptStatus(pCtxt->module, EUSCI_B_SPI_TRANSMIT_INTERRUPT)));

      rxData = SPI_receiveData(pCtxt->module);

I can correct this using my own definition for the interrupt mask bits. 

However I would like to know if  am I misunderstanding the comments about the "mask" macros, or is there a bug in the macro definition?

Or the other possibility did I accidentally copy/paste over the macro when digging into the header files for the macros?

  • Hello Mark,

    Please refer the example in the folder "./examples/nortos/MSP_EXP432P401R/driverlib/spi_3wire_incrementing_data-master".

    In the example the define used for check what triggered interrupt is EUSCI_B_SPI_RECEIVE_INTERRUPT and not EUSCI_SPI_RECEIVE_INTERRUPT.

    Thanks,
    Sai
  • It looks like the documentation of the API "SPI_getEnabledInterruptStatus" might be wrong. I will file a bug report on the documentation.

    Thanks,
    Sai
  • Thanks Sai,

    I ended up creating my own generic flag macros, because I'm using a common HWI for the EUSCIA and EUSCIB SPI interfaces. Based on the register structure, I can get away with using EUSCI_B_SPI_RECEIVE_INTERRUPT and EUSCI_B_SPI_TRANSMIT_INTERRUPT for the EUSCIA ports because those bits live in the same location in (A and B EUSCI ports).

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