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MSP430F417: Crystal oscillator issues

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Replies: 4

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Part Number: MSP430F417

hello TI:

            mcu msp430f417,Crystal oscillator does not vibrate,Crystal parameters:32768hz Cl 12.5pF,

1.Configure internal 10P capacitors to work properly.

2.Configure the internal 1P capacitor, externally connect 2 22P capacitors, it can't work normally.  LFOF=1,why?

If we choose method 1, is it OK?

  • Hello,

    Are you setting XTS_FLL=0 in your code? I would recommend using external load capacitors for the crystal for higher precision, since the internal load capacitors may vary slightly between devices. I'm assuming when you use both internal and external load capacitors, you're effective load capacitance may not be correct.

    Please read through the MSP430 32kHz Crystal Oscillators app note, specifically Section 2.1 Effective Load Capacitance.

    Regards,

    James

    MSP Customer Applications

    Check out our new Answers to Common Sigma-Delta ADC Questions on MSP MCUs app note!

  • In reply to James Evans:

    hello james,

         Thank you for your reply.

        in my code  XTS_FLL=0,We try to set “FLL_CTL0=0”,External capacitor configuration 22P,LFOF =1; reset is useless,why?

        If the clock is accurate, we want it most, but I can't start it. I don't want to see it. If the clock requirements are not so harsh, choose whether the internal crystal is feasible.

    Regards

  • In reply to faqu chen44:

    Hello,

    Setting XTS_FLL= 0 is good for LF operation with a watch crystal. Looking at page 304 in the MSP430x4xx User's Guide, setting FLL_CTL0 = 0 may cause an issue, since XT2OF doesn't exist for MSP430x41x devices and bits 3 through 0 of FLL_CTL0 are read-only. Try using the bit-wise OR operand (|=)rather than just the equal sign (=). For example, try  FLL_CTL0|=XCAP14PF;

    If you're seeing LFOF = 1, then there's definitely an oscillator fault. If your crystal's load capacitance is 12.5pF, then according to the effective load capacitance equation (Equation 3) in SLAA322, you'll need two 23pF capacitors (assuming your PCB has approximately 2nF parasitic capacitance). You're using two 22pF capacitors, which should be close enough unless your PCB has higher parasitic capacitance. I'm still not sure why you're seeing an oscillator fault flag, LFOF = 1.

    In SLAA322, you can see how the frequency of the crystal depends on the effective load capacitance.

    For your case, if XCAP10PF works, then I'd just use that until you can dig more deeply into the issue and follow all the recommendations in SLAA322. Unfortunately, this device is quite old. Have you considered using our newer FRAM devices, such as the MSP430FR4133? The FR4xx devices don't seem to have integrated load capacitors though but may have other advantages over the older F4xx devices for your application.

    Migrating From the MSP430F4xx Family to the MSP430FR4xx/FR2xx Family

    Regards,

    James

    MSP Customer Applications

    Check out our new Answers to Common Sigma-Delta ADC Questions on MSP MCUs app note!

  • In reply to James Evans:

    As a follow-up, perhaps you can leverage one of our code examples for the MSP430F417. After startup, it configures the internal load caps and then outputs MCLK and ACLK on P1.1 and P1.5. This way, you could use different XCAP values and measure ACLK's frequency on one of these pins. This is actually a better method than probing the crystal directly (since the probe pins have capacitance too). I do see that the code example sets FLL_CTL0 = 0, so my earlier concern about this may not be correct.

    fet430_clks_01.c

    /* --COPYRIGHT--,BSD_EX
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     *    from this software without specific prior written permission.
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     *
     *******************************************************************************
     * 
     *                       MSP430 CODE EXAMPLE DISCLAIMER
     *
     * MSP430 code examples are self-contained low-level programs that typically
     * demonstrate a single peripheral function or device feature in a highly
     * concise manner. For this the code may rely on the device's power-on default
     * register values and settings such as the clock configuration and care must
     * be taken when combining code from several examples to avoid potential side
     * effects. Also see www.ti.com/grace for a GUI- and www.ti.com/msp430ware
     * for an API functional library-approach to peripheral configuration.
     *
     * --/COPYRIGHT--*/
    //******************************************************************************
    //  MSP-FET430P410 Demo - FLL+, Output MCLK, ACLK Using 32kHz XTAL and DCO
    //
    //  Description: This program outputs buffered MCLK and ACLK on port pins
    //  P1.1 and P1.5.
    //  ACLK = LFXT1 = 32768Hz, MCLK = SMCLK = default DCO = 32 x ACLK = 1048576Hz
    //  //* An external watch crystal between XIN & XOUT is required for ACLK *//	
    //
    //                MSP430F413
    //            -----------------
    //        /|\|              XIN|-
    //         | |                 | 32kHz
    //         --|RST          XOUT|-
    //           |                 |
    //           |        P1.1/MCLK|-->MCLK = 1048576Hz
    //           |        P1.5/ACLK|-->ACLK = 32kHz
    //
    //  M. Buccini
    //  Texas Instruments Inc.
    //  Feb 2005
    //  Built with CCE Version: 3.2.0 and IAR Embedded Workbench Version: 3.21A
    //*****************************************************************************
    #include <msp430.h>
    
    int main(void)
    {
      WDTCTL = WDTPW + WDTHOLD;                 // Stop watchdog timer
      FLL_CTL0 = XCAP14PF;                      // Configure load caps
    
      P1DIR = 0x22;                             // P1.1,5 to output direction
      P1SEL = 0x22;                             // P1.1,5 to output MCLK & ACLK
    
      while(1);                                 // Loop in place
    }

    Regards,

    James

    MSP Customer Applications

    Check out our new Answers to Common Sigma-Delta ADC Questions on MSP MCUs app note!

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