Hi community member,
My customers have asked about the DCO generator and the FLL function of MSP430F6726.
Please check the following and let me know.
<Background>
In my customer's system, the Timer_A capture mode is used to capture the timer counter.
The input clock (TASSEL) uses DCO (SMCLK), and 250 kHz is input by the divider (ID) of Timer_A.
When capturing, an error of the capture value occurs irregularly.This error is 0.2% to 0.3% off the customer's target value.
If FLL is invalidated, such error no longer appears.
Therefore, my customer think that the jitter of the FLL is large.
<Question 1>
a. What is the circuit configuration of the "DC Generator" with FLL removed? What is the operating principle of the DCO?
b. Please tell me the accuracy of the internal DC oscillator itself.
c. Does it affect operating frequency due to aged deterioration?
In question 1, customers want to know the structure of DCO.
<Question 2>
a. What are the specifications that can not be guaranteed if the FLL function is disabled?
In my recognition, I think that the following issue come up if FLL is disabled.
Please tell me about a different or additional concern.
- MSP430 Device Individual Difference
- DCO frequency temperature drift and DCO frequency voltage drift in Table 5-10 are not corrected
b. Please tell me the procedure to disable the FLL function.
I think that it can be invalidated by setting SCG0 to 1.
Please tell me if there are other steps necessary to invalidate FLL.
（For example, setting a settling time etc...）
c. Please tell me if there is a way to reduce FLL correction jitter.
Please confirm.
Cruijff
